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REJ09B0164-0210
16
R8C/14 Group, R8C/15 Group
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES
All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).
Rev.2.10 Revision Date:Jan 19, 2006
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6. 7.
8.
These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the R8C/14 Group, R8C/15 Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2.
Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
*1
Symbol XXX Address XXX After Reset 00h
0
*5
Bit Symbol
XXX0
Bit Name
XXX Bit
b1 b0
Function
1 0: XXX 0 1: XXX 1 0: Avoid this setting 1 1: XXX
RW RW
*2
XXX1
RW
(b2)
Nothing is assigned. When write, should set to "0". When read, its content is indeterminate.
*3
RW
(b3)
Reserved Bit
Must set to "0"
*4
XXX4
XXX Bit
Function varies depending on each operation mode
RW
XXX5
WO
XXX6 0: XXX 1: XXX
RW
XXX7
XXX Bit
RO
*1 Blank:Set to "0" or "1" according to the application 0: Set to "0" 1: Set to "1" X: Nothing is assigned *2 RW: Read and write RO: Read only WO: Write only -: Nothing is assigned *3 *Reserved bit Reserved bit. Set to specified value. *4 *Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to "0" when writing to this bit. *Do not set to this value The operation is not guaranteed when a value is set. *Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode. *5 Follow the text in each manual for binary and hexadecimal notations.
3.
M16C Family Documents
The following documents were prepared for the M16C family.(1) Document Short Sheet Data Sheet Hardware Manual Contents Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts). *Refer to the application note for how to use peripheral functions. Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note * Usage and application examples of peripheral functions * Sample programs * Introduction to the basic functions in the M16C family * Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc.
NOTES: 1. Before using this material, please visit the our website to verify that this is the most updated document available.
Table of Contents
SFR Page Reference 1. Overview
1.1 1.2 1.3 1.4 1.5 1.6
B-1 1
Applications .................................................................................................1 Performance Overview................................................................................2 Block Diagram .............................................................................................4 Product Information .....................................................................................5 Pin Assignments..........................................................................................7 Pin Description ............................................................................................8
2.
Central Processing Unit (CPU)
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
10
Data Registers (R0, R1, R2 and R3).........................................................11 Address Registers (A0 and A1).................................................................11 Frame Base Register (FB) ........................................................................11 Interrupt Table Register (INTB) .................................................................11 Program Counter (PC) ..............................................................................11 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).....................11 Static Base Register (SB)..........................................................................11 Flag Register (FLG)...................................................................................11 Carry Flag (C).....................................................................................11 Debug Flag (D) ...................................................................................11 Zero Flag (Z).......................................................................................11 Sign Flag (S).......................................................................................11 Register Bank Select Flag (B) ............................................................11 Overflow Flag (O) ...............................................................................11 Interrupt Enable Flag (I Flag)..............................................................12 Stack Pointer Select Flag (U Flag) .....................................................12 Processor Interrupt Priority Level (IPL) ..............................................12 Reserved Bit .......................................................................................12
2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 2.8.8 2.8.9 2.8.10
3.
Memory
3.1 3.2
13
R8C/14 Group ...........................................................................................13 R8C/15 Group ...........................................................................................14
A-1
4. 5.
Special Function Register (SFR) Reset
5.1 5.1.1 5.1.2 5.2 5.3 5.4 5.5 5.6
15 19
Hardware Reset ........................................................................................21 When the power supply is stable........................................................21 Power on ............................................................................................21
Power-On Reset Function .........................................................................23 Voltage Monitor 1 Reset ...........................................................................24 Voltage Monitor 2 Reset............................................................................24 Watchdog Timer Reset..............................................................................24 Software Reset..........................................................................................24
6.
Voltage Detection Circuit
6.1 6.1.1 6.1.2 6.2 6.3
25
Monitoring VCC Input Voltage...................................................................31 Monitoring Vdet1 ................................................................................31 Monitoring Vdet2 ................................................................................31
Voltage Monitor 1 Reset............................................................................32 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset .........................33
7.
Processor Mode
7.1
35
Types of Processor Mode .........................................................................35
8. 9.
Bus Clock Generation Circuit
9.1 9.2
37 38
Main Clock.................................................................................................45 On-Chip Oscillator Clock ...........................................................................46 Low-Speed On-Chip Oscillator Clock .................................................46 High-Speed On-Chip Oscillator Clock ................................................46 System Clock......................................................................................47 CPU Clock ..........................................................................................47 Peripheral Function Clock (f1, f2, f4, f8, f32) ......................................47 fRING and fRING128..........................................................................47 fRING-fast...........................................................................................47 fRING-S ..............................................................................................47
9.2.1 9.2.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4
CPU Clock and Peripheral Function Clock................................................47
Power Control............................................................................................48
A-2
9.4.1 9.4.2 9.4.3 9.5 9.5.1
Normal Operating Mode .....................................................................48 Wait Mode ..........................................................................................49 Stop Mode ..........................................................................................51 How to Use Oscillation Stop Detection Function ................................53
Oscillation Stop Detection Function ..........................................................53
10. Protection 11. Interrupt
11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.4
55 56
Interrupt Overview .....................................................................................56 Types of Interrupts..............................................................................56 Software Interrupts .............................................................................57 Special Interrupts................................................................................58 Peripheral Function Interrupt ..............................................................58 Interrupts and Interrupt Vector............................................................59 Interrupt Control..................................................................................61 INT0 Interrupt .....................................................................................69 INT0 Input Filter..................................................................................70 INT1 Interrupt .....................................................................................71 INT3 Interrupt .....................................................................................72
INT Interrupt ..............................................................................................69
Key Input Interrupt.....................................................................................74 Address Match Interrupt ............................................................................76
12. Watchdog Timer
12.1 12.2
78
When Count Source Protection Mode Disabled........................................81 When Count Source Protection Mode Enabled.........................................82
13. Timers
13.1 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.2 13.2.1
83
Timer Mode ........................................................................................87 Pulse Output Mode.............................................................................88 Event Counter Mode...........................................................................90 Pulse Width Measurement Mode .......................................................92 Pulse Period Measurement Mode ......................................................95 Timer Mode ......................................................................................103
A-3
Timer X......................................................................................................84
Timer Z ......................................................................................................98
13.2.2 13.2.3 13.2.4 13.3 13.3.1 13.3.2
Programmable Waveform Generation Mode....................................105 Programmable One-shot Generation Mode .....................................108 Programmable Wait One-shot Generation Mode .............................111 Input Capture Mode..........................................................................121 Output Compare Mode .....................................................................123
Timer C....................................................................................................115
14. Serial Interface
14.1 14.1.1 14.1.2 14.1.3 14.2 14.2.1 14.2.2
125
Clock Synchronous Serial I/O Mode .......................................................130 Polarity Select Function....................................................................133 LSB First/MSB First Select Function ................................................133 Continuous Receive Mode ...............................................................134 CNTR0 Pin Select Function..............................................................138 Bit Rate.............................................................................................139
Clock Asynchronous Serial I/O (UART) Mode ........................................135
15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.1 15.2 15.3 15.4 15.5 15.1.1 15.2.1
140
Transfer Clock .........................................................................................149 Association between Transfer Clock Polarity, Phase and Data .......149 Association between Data I/O Pin and SS Shift Register.................151 SS Shift Register (SSTRSR) ...................................................................151 Interrupt Requests...................................................................................152 Communication Modes and Pin Functions..............................................153 Clock Synchronous Communication Mode .............................................154 Initialization in Clock Synchronous Communication Mode ...............154 Data Transmit ...................................................................................155 Data Receive ....................................................................................157 Data Transmit/Receive .....................................................................159 Initialization in 4-Wire Bus Communication Mode ............................161 Data Transmit ...................................................................................163 Data Receive ....................................................................................165 SCS Pin Control and Arbitration .......................................................167
15.5.1 15.5.2 15.5.3 15.5.4 15.6 15.6.1 15.6.2 15.6.3 15.6.4
Operation in 4-Wire Bus Communication Mode ......................................161
16. A/D Converter
16.1
168
One-Shot Mode .......................................................................................172
A-4
16.2 16.3 16.4 16.5 16.6
Repeat Mode...........................................................................................174 Sample and Hold.....................................................................................176 A/D Conversion Cycles ...........................................................................176 Internal Equivalent Circuit of Analog Input ..............................................177 Inflow Current Bypass Circuit ..................................................................178
17. Programmable I/O Ports
17.1 17.2 17.3 17.4 17.5
179
Functions of Programmable I/O Ports .....................................................179 Effect on Peripheral Functions ................................................................179 Pins Other than Programmable I/O Ports................................................179 Port setting ..............................................................................................186 Unassigned Pin Handling ........................................................................190
18. Flash Memory Version
18.1 18.2 18.3
191
Overview .................................................................................................191 Memory Map ...........................................................................................193 Functions To Prevent Flash Memory from Rewriting ..............................195 ID Code Check Function ..................................................................195 ROM Code Protect Function ............................................................196 EW0 Mode........................................................................................198 EW1 Mode........................................................................................198 Software Commands ........................................................................205 Status Register .................................................................................209 Full Status Check .............................................................................210 ID Code Check Function ..................................................................212 ROM Code Protect Function ............................................................216
18.3.1 18.3.2 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.5 18.6 18.5.1 18.6.1
CPU Rewrite Mode..................................................................................197
Standard Serial I/O Mode........................................................................212 Parallel I/O Mode.....................................................................................216
19. Electrical Characteristics 20. Precautions
20.1 20.1.1 20.1.2 20.2
217 235
Stop Mode and Wait Mode......................................................................235 Stop Mode ........................................................................................235 Wait Mode ........................................................................................235
Interrupts .................................................................................................236
A-5
20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.3 20.3.1 20.3.2 20.4 20.4.1 20.4.2 20.4.3 20.4.4 20.5 20.6 20.7 20.8 20.9
Reading Address 00000h .................................................................236 SP Setting.........................................................................................236 External Interrupt and Key Input Interrupt ........................................236 Watchdog Timer Interrupt.................................................................236 Changing Interrupt Factor.................................................................237 Changing Interrupt Control Register.................................................238 Oscillation Stop Detection Function..................................................239 Oscillation Circuit Constants.............................................................239 Timers X and Z .................................................................................240 Timer X .............................................................................................240 Timer Z .............................................................................................241 Timer C.............................................................................................241
Clock Generation Circuit .........................................................................239
Timers .....................................................................................................240
Serial Interface ........................................................................................242 Clock Synchronous Serial I/O (SSU) with Chip Select............................243 Access Registers Associated with SSU ...........................................243 A/D Converter..........................................................................................244 Flash Memory Version ............................................................................245 CPU Rewrite Mode...........................................................................245 Insert a bypass capacitor between VCC and VSS pins as the countermeasures against noise and latch-up...................................248 Countermeasures against Noise Error of Port Control Registers.....248 Noise .......................................................................................................248
20.6.1
20.8.1 20.9.1 20.9.2
21. Precaution for On-chip Debugger Appendix 1. Package Dimensions
249 250
Appendix 2. Connecting Example between Serial Writer and On-Chip Debugging Emulator 251 Appendix 3. Example of Oscillation Evaluation Circuit Register Index 252 253
A-6
SFR Page Reference
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol Page Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah Count Source Protection Mode Register INT0 Input Filter Select Register High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 CSPR INT0F HRA0 HRA1 HRA2 80 69 43 44 44 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Register Symbol Page
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PM0 PM1 CM0 CM1 AIER PRCR OCD WDTR WDTS WDC RMAD0
35 36 40 41 77 55 42 80 80 79 77
Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU Interrupt Control Register Compare 1 Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register
KUPIC ADIC SSUAIC CMP1IC S0TIC S0RIC
61 61 61 61 61 61
Address Match Interrupt Register 1
RMAD1
77
Timer X Interrupt Control Register Timer Z Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register Timer C Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register
TXIC TZIC INT1IC INT3IC TCIC CMP0IC INT0IC
61 61 61 61 61 61 62
Voltage Detection Register 1 Voltage Detection Register 2
VCA1 VCA2
28 28
Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register
VW1C VW2C
29 30
NOTES: 1. Blank columns are all reserved space. No access is allowed.
B-1
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
Register Timer Z Mode Register
Symbol TZMR
Page 99
Timer Z Waveform Output Control Register Prescaler Z Timer Z Secondary Timer Z Primary
PUM PREZ TZSC TZPR
101 100 100 100
Timer Z Output Control Register Timer X Mode Register Prescaler X Timer X Timer Count Source Set Register Timer C
TZOC TXMR PREX TX TCSS TC
101 85 86 86 86,102 117
External Input Enable Register Key Input Enable Register Timer C Control Register 0 Timer C Control Register 1 Capture, Compare 0 Register Compare 1 Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register
INTEN KIEN TCC0 TCC1 TM0 TM1 U0MR U0BRG U0TB U0C0 U0C1 U0RB
69 75 118 119 117 117 128 127 127 128 129 127
UART Transmit/Receive Control Register 2
UCON
129
SS Control Register H SS Control Register L SS Mode Register SS Enable Register SS Status Register SS Mode Register 2 SS Transmit Data Register SS Receive Data Register
SSCRH SSCRL SSMR SSER SSSR SSMR2 SSTDR SSRDR
142 143 144 145 146 147 148 148
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 01B3h 01B4h 01B5h 01B6h 01B7h 0FFFFh
Register A/D Register
Symbol AD
Page 171
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
171 170 170
Port P1 Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P4 Direction Register
P1 PD1 P3 PD3 P4 PD4
184 184 184 184 184 184
Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register Timer C Output Control Register Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0 Optional Function Select Register
PUR0 PUR1 DRR TCOUT FMR4 FMR1 FMR0 OFS
185 185 185 120 201 201 200 79,196
NOTES: 1. Blank columns, 0100h to 01AFh and 01C0h to 02FFh are all reserved. No access is allowed.
B-2
R8C/14 Group, R8C/15 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ09B0164-0210 Rev.2.10 Jan 19, 2006
1.
Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 20-pin plastic molded LSSOP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. Furthermore, the data flash ROM (1KB x 2blocks) is embedded in the R8C/15 group. The difference between R8C/14 and R8C/15 groups is only the existence of the data flash ROM. Their peripheral functions are the same.
1.1
Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
Page 1 of 253
R8C/14 Group, R8C/15 Group
1. Overview
1.2
Performance Overview
Table 1.1 lists the Performance Outline of the R8C/14 Group and Table 1.2 lists the Performance Outline of the R8C/15 Group. Table 1.1 Performance Outline of the R8C/14 Group Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction 50ns(f(XIN)=20MHz, VCC=3.0 to 5.5V) Execution Time 100ns(f(XIN)=10MHz, VCC=2.7 to 5.5V) Operating Mode Single-chip Memory Space 1 Mbyte Memory Capacity See Table 1.3 R8C/14 Group Product Information Peripheral Port I/O port : 13 pins (including LED drive port), Function Input : 2 pins LED Drive Port I/O port: 4 pins Timer Timer X: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Circuits of input capture and output compare) Serial Interface 1 channel Clock synchronous serial I/O, UART Chip-Select Clock 1 channel Synchronous Serial I/O (SSU) A/D Converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog Timer 15 bits x1 channel (with prescaler) Reset start selectable, Count source protection mode Interrupt Internal: 9 factors, External: 4 factors, Software: 4 factors, Priority level: 7 levels Clock Generation Circuit 2 circuits * Main clock oscillation circuit (Equipped with a built-in feedback resistor) * On-chip oscillator (high speed, low speed) Equipped with frequency adjustment function on highspeed on-chip oscillator Oscillation Stop Detection Main clock oscillation stop detection function Function Voltage Detection Circuit Included Power-On Reset Circuit Included Electric Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz) Characteristics VCC=2.7 to 5.5V (f(XIN)=10MHz) Power Consumption Typ. 9mA (VCC=5.0V, f(XIN)=20MHz) Typ. 5mA (VCC=3.0V, f(XIN)=10MHz) Typ. 35A (VCC=3.0V, wait mode, peripheral clock off) Typ. 0.7A (VCC=3.0V, stop mode) Flash Memory Program/Erase Supply VCC=2.7 to 5.5V Voltage Program/Erase Endurance 100 times Operating Ambient Temperature -20 to 85C -40 to 85C (D Version) Package 20-pin plastic mold LSSOP
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
Page 2 of 253
R8C/14 Group, R8C/15 Group
1. Overview
Table 1.2
Performance Outline of the R8C/15 Group Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction 50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V) Execution Time 100ns (f(XIN)=10MHz, VCC=2.7 to 5.5V) Operating Mode Single-chip Memory Space 1 Mbyte Memory Capacity See Table 1.4 R8C/15 Group Product Information Peripheral Port I/O : 13 pins (including LED drive port), Function Input : 2 pins LED drive port I/O port: 4 pins Timer Timer X: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Circuits of input capture and output compare) Serial Interface 1 channel Clock synchronous serial I/O, UART Chip-select clock 1 channel synchronous serial I/O (SSU) A/D Converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog Timer 15 bits x 1 channel (with prescaler) Reset start selectable, Count source protection mode Interrupt Internal: 9 factors, External: 4 factors, Software: 4 factors Priority level: 7 levels Clock Generation Circuit 2 circuits * Main clock generation circuit (Equipped with a built-in feedback resistor) * On-chip oscillator (high speed, low speed) Equipped with frequency adjustment function on highspeed on-chip oscillator Oscillation Stop Detection Main clock oscillation stop detection function Function Voltage Detection Circuit Included Power on Reset Circuit Included Electric Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz) Characteristics VCC=2.7 to 5.5V (f(XIN)=10MHz) Power Consumption Typ. 9mA (VCC=5.0V, f(XIN)=20MHz) Typ. 5mA (VCC=3.0V, f(XIN)=10MHz) Typ. 35A (VCC=3.0V, wait mode, peripheral clock off) Typ. 0.7A (VCC=3.0V, stop mode) Flash Memory Program/Erase Supply VCC=2.7 to 5.5V Voltage Program/Erase Endurance 10,000 times (Data flash) 1,000 times (Program ROM) Operating Ambient Temperature -20 to 85C -40 to 85C (D Version) Package 20-pin plastic mold LSSOP
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
Page 3 of 253
R8C/14 Group, R8C/15 Group
1. Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
4
1
2
I/O port Peripheral Function
Timer
Port P1
Port P3
Port P4
A/D Converter (10 bits x 4 channels) UART or Clock Synchronous Serial I/O (8 bits x 1 channel) Chip-Select Clock Synchronous Serial I/O (8 bits x 1 channel)
Timer X (8 bits) Timer Z (8 bits) Timer C (16 bits)
System Clock Generator XIN-XOUT High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator
Watchdog Timer (15 bits)
R8C/Tiny Series CPU Core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM(1)
RAM(2)
Multiplier
NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type.
Figure 1.1
Block Diagram
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
Page 4 of 253
R8C/14 Group, R8C/15 Group
1. Overview
1.4
Product Information
Table 1.3 lists the Product Information of R8C/14 Group and Table 1.4 lists the Product Information of R8C/15 Group. Table 1.3 Product Information of R8C/14 Group ROM capacity 8 Kbytes 12 Kbytes 16 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes RAM capacity 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte Package type PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A As of Jan 2006 Remarks Flash memory version
Type No. R5F21142SP R5F21143SP R5F21144SP R5F21142DSP R5F21143DSP R5F21144DSP
D version
Type No.
R 5 F 21 14 4 D SP
Package type: SP : PLSP0020JB-A Grouping D : Operating Ambient Temperature -40C to 85C No Symbol : Operating Ambient Temperature -20C to 85C ROM capacity 2 : 8KB 3 : 12KB 4 : 16KB R8C/14 Group R8C/Tiny Series Memory Type F : Flash Memory Version Renesas MCU Renesas Semiconductors
Figure 1.2
Part Number, Memory Size and Package of R8C/14 Group
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R8C/14 Group, R8C/15 Group
1. Overview
Table 1.4 Type No.
Product Information of R8C/15 Group ROM capacity Program ROM Data flash 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 RAM capacity 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte Package type PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A
As of Jan 2006 Remarks Flash memory version
R5F21152SP R5F21153SP R5F21154SP R5F21152DSP R5F21153DSP R5F21154DSP
D version
Type No.
R 5 F 21 15 4 D SP
Package type: SP : PLSP0020JB-A Grouping D : Operating Ambient Temperature -40C to 85C No Symbol : Operating Ambient Temperature -20C to 85C ROM Capacity 2 : 8KB 3 : 12KB 4 : 16KB R8C/15 Group R8C/Tiny Series Memory Type F : Flash Memory Version Renesas MCU Renesas Semiconductors
Figure 1.3
Part Number, Memory Size and Package of R8C/15 Group
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R8C/14 Group, R8C/15 Group
1. Overview
1.5
Pin Assignments
Figure 1.4 shows the PLSP0020JB-A Package Pin Assignment (top view).
PIN Assignment (top view)
P3_5/SSCK/CMP1_2 P3_7/CNTR0/SSO RESET XOUT/P4_7(1) VSS/AVSS XIN/P4_6 VCC MODE P4_5/INT0 P1_7/CNTR00/INT10
1 2 3
20 19 18
P3_4/SCS/CMP1_1 P3_3/TCIN/INT3/SSI/CMP1_0 P1_0/KI0/AN8/CMP0_0 P1_1/KI1/AN9/CMP0_1 AVCC/VREF P1_2/KI2/AN10/CMP0_2 P1_3/KI3/AN11/TZOUT P1_4/TXD0 P1_5/RXD0/CNTR01/INT11 P1_6/CLK0
R8C/14 Group R8C/15 Group
4 5 6 7 8 9 10
17 16 15 14 13 12 11
NOTES: 1. P4_7 is a port for the input. Package: PLSP0020JB-A(20P2F-A)
Figure 1.4 PLSP0020JB-A Package Pin Assignment (top view)
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R8C/14 Group, R8C/15 Group
1. Overview
1.6
Pin Description
Table 1.5 lists the Pin Description and Table 1.6 lists the Pin Name Information by Pin Number. Table 1.5 Pin Description Pin name VCC VSS I/O type I I Description Apply 2.7V to 5.5V to the VCC pin. Apply 0V to the VSS pin Power supply input pins to A/D converter. Connect AVCC to VCC. Apply 0V to AVSS. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU Connect this pin to VCC via a resistor These pins are provided for the main clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. INT interrupt input pins Key input interrupt input pins Timer X I/O pin Timer X output pin. Timer Z output pin Timer C input pin Timer C output pins. Transfer clock I/O pin. Serial data input pin. Serial data output pin. Data I/O pin. Chip-select signal I/O pin. Clock I/O pin. Data I/O pin. Reference voltage input pin to A/D converter Connect VREF to VCC Analog input pins to A/D converter These are CMOS I/O ports. Each port contains an I/O select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull-up resistor or not by program. P1_0 to P1_3 also function as LED drive ports. Port for input-only
Function Power Supply Input
Analog Power Supply AVCC Input AVSS Reset Input MODE Main Clock Input Main Clock Output RESET MODE XIN XOUT
I I I O
INT Interrupt Key Input Interrupt Timer X Timer Z Timer C
INT0, INT1, INT3 KI0 to KI3 CNTR0 CNTR0 TZOUT TCIN CMP0_0 to CMP0_2, CMP1_0 to CMP1_2
I I I/O O O I O I/O I O I/O I/O I/O I/O I I I/O
Serial Interface
CLK0 RXD0 TXD0
SSU
SSI SCS SSCK SSO
Reference Voltage Input A/D Converter I/O Port
VREF AN8 to AN11 P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5
Input Port I: Input O: Output
P4_6, P4_7 I/O: Input and output
I
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1. Overview
Table 1.6
Pin Name Information by Pin Number I/O Pin of Peripheral Function Clock Synchronous Serial Timer Interface Serial I/O with Chip Select CMP1_2 SSCK SSO CNTR0
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Control Pin
Port
Interrupt
A/D Converter
P3_5 P3_7 RESET XOUT VSS/AVSS XIN VCC MODE P4_7 P4_6
P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 AVCC/VREF P1_1 P1_0 P3_3 P3_4
INT0 INT10 INT11 KI3 KI2 KI1 KI0 INT3 CNTR00 CNTR01 TZOUT CMP0_2 CMP0_1 CMP0_0 TCIN/CMP1_0 CMP1_1 SSI SCS CLK0 RXD0 TXD0 AN11 AN10 AN9 AN8
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2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R1H (high-order of R1)
R0L (low-order of R0) R1L (low-order of R1) Data Registers (1)
R2 R3 A0 A1 FB
b19 b15 b0
Address Registers (1) Frame Bass Register (1)
INTBH
INTBL
Interrupt Table Register
The 4-high order bits of INTB are INTBH and the 16-low bits of INTB are INTBL.
b19 b0
PC
Program Counter
b15
b0
USP ISP SB
b15 b0
User Stack Pointer Interrupt Stack Pointer Static Base Register
FLG
b15 b8 b7 b0
Flag Register
IPL
U I OBSZDC
Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Bit Processor Interrupt Priority Level Reserved Bit
NOTES: 1. A register bank comprises these registers. Two sets of register banks are provided
Figure 2.1
CPU Register
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2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2
Debug Flag (D)
The D flag is for debug only. Set to "0".
2.8.3
Zero Flag (Z)
The Z flag is set to "1" when an arithmetic operation resulted in 0; otherwise, "0".
2.8.4
Sign Flag (S)
The S flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, "0".
2.8.5
Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is "0". The register bank 1 is selected when this flag is set to "1".
2.8.6
Overflow Flag (O)
The O flag is set to "1" when the operation resulted in an overflow; otherwise, "0".
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2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I Flag)
The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0", and are enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is set to "0", USP is selected when the U flag is set to "1". The U flag is set to "0" when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
When write to this bit, set to "0". When read, its content is indeterminate.
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3. Memory
3.
3.1
Memory
R8C/14 Group
Figure 3.1 is a Memory Map of R8C/14 Group. The R8C/14 group provides 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses beginning with address 0FFFFh. For example, a 16Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
00000h
SFR
(See 4. Special Function Register (SFR))
002FFh
00400h
Internal RAM
0XXXXh 0FFDCh
Undefined Instruction Overflow BRK Instruction Address Match Single Step
Watchdog Timer*Oscillation Stop Detection*Voltage Monitor 2
0YYYYh
Internal ROM
0FFFFh 0FFFFh
Address Break (Reserved) Reset
Expansion Area
FFFFFh
NOTES: 1. Blank spaces are reserved. No access is allowed. Internal ROM Part Number R5F21144SP, R5F21144DSP R5F21143SP, R5F21143DSP R5F21142SP, R5F21142DSP Size 16 Kbytes 12 Kbytes 8 Kbytes 0YYYYh 0C000h 0D000h 0E000h Internal RAM Size 1 Kbytes 768 bytes 512 bytes 0XXXXh 007FFh 006FFh 005FFh
Figure 3.1
Memory Map of R8C/14 Group
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R8C/14 Group, R8C/15 Group
3. Memory
3.2
R8C/15 Group
Figure 3.2 is a Memory Map of R8C/15 Group. The R8C/15 group provides 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
00000h
SFR
(See 4. Special Function Register (SFR))
002FFh 00400h
Internal RAM
0XXXXh
02400h 02BFFh
Internal ROM (Data Flash)(1)
0FFDCh
Undefined Instruction Overflow BRK Instruction Address Match Single Step
Watchdog Timer * Oscillation Stop Detection * Voltage Monitor 2
0YYYYh
Internal ROM (Program ROM)
0FFFFh 0FFFFh
Address Break (Reserved) Reset
Expansion Area
FFFFFh
NOTES: 1. The data flash block A (1 Kbyte) and block B (1 Kbyte) are shown. 2. Blank spaces are reserved. No access is allowed. Internal ROM Part Number R5F21154SP, R5F21154DSP R5F21153SP, R5F21153DSP R5F21152SP, R5F21152DSP Size 16K bytes 12K bytes 8K bytes 0YYYYh 0C000h 0D000h 0E000h Internal RAM Size 1K byte 768 bytes 512 bytes 0XXXXh 007FFh 006FFh 005FFh
Figure 3.2
Memory Map of R8C/15 Group
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4. Special Function Register (SFR)
4.
Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information. Table 4.1 SFR Information(1)(1)
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol After reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PM0 PM1 CM0 CM1 AIER PRCR OCD WDTR WDTS WDC RMAD0
00h 00h 01101000b 00100000b 00h 00h 00000100b XXh XXh 00011111b 00h 00h X0h 00h 00h X0h
Address Match Interrupt Register 1
RMAD1
Count Source Protection Mode Register INT0 Input Filter Select Register High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2
CSPR INT0F HRA0 HRA1 HRA2
00h 00h 00h When shipping 00h
Voltage Detection Register 1(2) Voltage Detection Register 2(2)
VCA1 VCA2
00001000b 00h(3) 01000000b(4)
Voltage Monitor 1 Circuit Control Register (2) Voltage Monitor 2 Circuit Control Register (5)
VW1C VW2C
0000X000b(3) 0100X001b(4) 00h
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. Software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect this register. 3. Owing to Hardware reset. 4. Owing to Power-on reset or the voltage monitor 1 reset. 5. Software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect the b2 and b3.
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R8C/14 Group, R8C/15 Group Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
4. Special Function Register (SFR)
SFR Information(2)(1)
Register Symbol After reset
Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU Interrupt Control Register Compare 1 Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register
KUPIC ADIC SSUAIC CMP1IC S0TIC S0RIC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b
Timer X Interrupt Control Register Timer Z Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register Timer C Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register
TXIC TZIC INT1IC INT3IC TCIC CMP0IC INT0IC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed.
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R8C/14 Group, R8C/15 Group Table 4.3
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
4. Special Function Register (SFR)
SFR Information(3)(1)
Register Timer Z Mode Register Symbol TZMR After reset 00h
Timer Z Waveform Output Control Register Prescaler Z Register Timer Z Secondary Register Timer Z Primary Register
PUM PREZ TZSC TZPR
00h FFh FFh FFh
Timer Z Output Control Register Timer X Mode Register Prescaler X Register Timer X Register Timer Count Source Setting Register Timer C Register
TZOC TXMR PREX TX TCSS TC
00h 00h FFh FFh 00h 00h 00h
External Input Enable Register Key Input Enable Register Timer C Control Register 0 Timer C Control Register 1 Capture, Compare 0 Register Compare 1 Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register
INTEN KIEN TCC0 TCC1 TM0 TM1 U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h 00h 00h 00h 00h 00h(2) FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh
UART Transmit/Receive Control Register 2
UCON
00h
SS Control Register H SS Control Register L SS Mode Register SS Enable Register SS Status Register SS Mode Register 2 SS Transmit Data Register SS Receive Data Register
SSCRH SSCRL SSMR SSER SSSR SSMR2 SSTDR SSRDR
00h 7Dh 18h 00h 00h 00h FFh FFh
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. When output compare mode (the TCC13 bit in the TCC1 register = 1) is selected, the value after reset is "FFFFh".
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R8C/14 Group, R8C/15 Group Table 4.4
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 01B3h 01B4h 01B5h 01B6h 01B7h 0FFFFh
4. Special Function Register (SFR)
SFR Information(4)(1)
Register A/D Register Symbol AD After reset XXh XXh
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
00h 00000XXXb 00h
Port P1 Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P4 Direction Register
P1 PD1 P3 PD3 P4 PD4
XXh 00h XXh 00h XXh 00h
Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register Timer C Output Control Register Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0 Optional Function Select Register
PUR0 PUR1 DRR TCOUT FMR4 FMR1 FMR0 OFS
00XX0000b XXXXXX0Xb 00h 00h 01000000b 1000000Xb 00000001b (2)
X: Undefined NOTES: 1. Blank columns, 0100h to 01B2h and 01B8h to 02FFh are all reserved. No access is allowed. 2. The OFS register cannot be changed by program. Use a flash programmer to write to it.
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5. Reset
5.
Reset
There are resets: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset and software reset. Table 5.1 lists the Reset Name and Factor. Table 5.1 Reset Name and Factor Reset Name Hardware Reset Power-On Reset Voltage Monitor 1 Reset Voltage Monitor 2 Reset Watchdog Timer Reset Software Reset Factor Input voltage of RESET pin is held "L" VCC rises VCC falls (monitor voltage : Vdet1) VCC falls (monitor voltage : Vdet2) Underflow of watchdog timer Write "1" to PM03 bit in PM0 register
RESET
Hardware Reset
SFR
VCA26, VW1C0 and VW1C6 bits
VCC
Power-On Reset Circuit
Power-On Reset
Voltage Detection Circuit
Voltage Monitor 1 Reset Voltage Monitor 2 Reset
SFR
VCA13, VCA27, VW1C1, VW1C2, VW1F0, VW1F1, VW1C7, VW2C2 and VW2C3 bits
Watchdog Timer
Watchdog Timer Reset
CPU
Software Reset
Pin, CPU and SFR other than above
VCA13 : Bit in VCA1 register VCA26, VCA27 : Bits in VCA2 register VW1C0 to VW1C2, VW1F0, VW1F1, VW1C6, VW1C7 : Bits in VW1C register VW2C2, VW2C3 bits : Bits in VW2C register
Figure 5.1
Block Diagram of Reset Circuit
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R8C/14 Group, R8C/15 Group Table 5.2 shows the Pin Status after Reset, Figure 5.2 shows CPU Register Status after Reset and Figure 5.3 shows Reset Sequence. Table 5.2 Pin Status after Reset Pin Status Input Port Input Port Input Port
5. Reset
Pin Name P1 P3_3 to P3_5, P3_7 P4_5 to P4_7
b15
b0
0000h 0000h 0000h 0000h 0000h 0000h 0000h
b19 b0
Data Register(R0) Data Register(R1) Data Register(R2) Data Register(R3) Address Register(A0) Address Register(A1) Frame Base Register(FB)
00000h Content of addresses 0FFFEh to 0FFFCh
b15 b0
Interrupt Table register(INTB) Program Counter(PC)
0000h 0000h 0000h
b15 b0
User Stack Pointer(USP) Interrupt Stack Pointer(ISP) Static Base Register(SB)
0000h
b15 b8 b7 b0
Flag Register(FLG)
IPL
U I OBSZDC
Figure 5.2
CPU Register Status after Reset
fRING-S 20 cycles or above are needed(1) Internal Reset Signal Flash memory activated time (CPU Clock x 72 Cycles) CPU Clock x 28 Cycles
CPU Clock 0FFFCh Address (Internal Address Signal) 0FFFDh NOTES: 1. This shows hardware reset Content of Reset Vector 0FFFEh
Figure 5.3
Reset Sequence
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5. Reset
5.1
Hardware Reset
A reset is applied using the RESET pin. When an "L" signal is applied to the RESET pin while the power supply voltage meets the recommended performance condition, the pins, CPU and SFR are reset (refer to Table 5.2 Pin Status after Reset). When the input level applied to the RESET pin changes "L" to "H", the program is executed beginning with the address indicated by the reset vector. After reset, the lowspeed on-chip oscillator clock divided-by-8 is automatically selected for the CPU clock. Refer to 4. Special Function Register (SFR) for the status of the SFR after reset. The internal RAM is not reset. If the RESET pin is pulled "L" during writing to the internal RAM, the internal RAM will be in indeterminate state. Figure 5.4 shows the Example of Hardware Reset Circuit and Operation and Figure 5.5 shows the Example of Hardware Reset Circuit (Use Example of External Power Supply Voltage Detection Circuit) and Operation.
5.1.1
When the power supply is stable
(1) Apply an "L" signal to the RESET pin. (2) Wait for 500s (1/fRING-Sx20). (3) Apply an "H" signal to the RESET pin.
5.1.2
Power on
(1) Apply an "L" signal to the RESET pin. (2) Let the power supply voltage increase until it meets the recommended performance condition. (3) Wait for td(P-R) or more until the internal power supply stabilizes (Refer to 19. Electrical Characteristics). (4) Wait for 500s (1/fRING-Sx20). (5) Apply an "H" signal to the RESET pin.
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5. Reset
VCC VCC 0V RESET RESET
2.7V
0.2VCC or below 0V td(P-R)+500s or above NOTES: 1. Refer to 19. Electrical Characteristics.
Figure 5.4
Example of Hardware Reset Circuit and Operation
Power Supply Voltage Detection Circuit
5V VCC 2.7V
RESET
VCC 0V 5V RESET
0V td(P-R)+500s or above Example when VCC=5V NOTES: 1. Refer to 19. Electrical Characteristics.
Figure 5.5
Example of Hardware Reset Circuit (Use Example of External Power Supply Voltage Detection Circuit) and Operation
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5. Reset
5.2
Power-On Reset Function
When the RESET pin is connected to the VCC pin via about 5k pull-up resistor and the VCC pin rises, the function is enabled and the microcomputer resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, always keep the voltage to the RESET pin 0.8VCC or more. When the input voltage to the VCC pin reaches to the Vdet1 level or above, count operation of the lowspeed on-chip oscillator clock starts. When the operation counts the low-speed on-chip oscillator clock for 32 times, the internal reset signal is held "H" and the microcomputer enters the reset sequence (See Figure 5.3). The low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU after reset. Refer to 4. Special Function Register (SFR) for the status of the SFR after power-on reset. The voltage monitor 1 reset is enabled after power-on reset. Figure 5.6 shows the Example of Power-On Reset Circuit and Operation.
VCC 0V
0.1V to 2.7V
VCC About 5k RESET
RESET 0V
0.8VCC or above
within td(P-R)
Vdet1(3) Vccmin Vpor2 Vpor1 tw(por1) tw(Vpor1-Vdet1) Sampling Time(1, 2) tw(por2) tw(Vpor2-Vdet1)
Vdet1(3)
Internal Reset Signal ("L" Valid) 1 x 32 fRING-S 1 x 32 fRING-S
NOTES: 1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time. 2. A sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit for details. 4. Refer to 19. Electrical Characteristics.
Figure 5.6
Example of Power-On Reset Circuit and Operation
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5. Reset
5.3
Voltage Monitor 1 Reset
A reset is applied using the built-in voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When the input voltage to the VCC pin reaches to the Vdet1 level or below, the pins, CPU and SFR are reset. And when the input voltage to the VCC pin reaches to the Vdet1 level or above, count operation of the low-speed on-chip oscillator clock starts. When the operation counts the low-speed on-chip oscillator clock for 32 times, the internal reset signal is held "H" and the microcomputer enters the reset sequence (See Figure 5.3). The low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU after reset. Refer to 4. Special Function Register (SFR) for the status of the SFR after voltage monitor 1 reset. The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet1 level or below during writing to the internal RAM, the internal RAM is in indeterminate state. Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.4
Voltage Monitor 2 Reset
A reset is applied using the built-in voltage detection 2 circuit. The voltage detection 2 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet2. When the input voltage to the VCC pin drops to the Vdet2 level or below, the pins, CPU and SFR are reset and the program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU clock. The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Register (SFR) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet2 level or below during writing to the internal RAM, the internal RAM is in indeterminate state. Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
5.5
Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to "1" (reset when watchdog timer underflows), the microcomputer resets its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU clock. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU clock. The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Register (SFR) for details. The internal RAM is not reset. When the watchdog timer underflows, the internal RAM is in indeterminate state. Refer to 12. Watchdog Timer for watchdog timer.
5.6
Software Reset
When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), the microcomputer resets its pins, CPU and SFR. The the program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU clock. The software reset does not reset some SFRs. Refer to 4. Special Function Register (SFR) for details. The internal RAM is not reset.
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6. Voltage Detection Circuit
6.
Voltage Detection Circuit
The voltage detection circuit is a circuit to monitor the input voltage to the VCC pin. This circuit monitors the VCC input voltage by the program. And the voltage monitor 1 reset, voltage monitor 2 interrupt and voltage monitor 2 reset can be used. Table 6.1 lists the Specification of Voltage Detection Circuit and Figures 6.1 to 6.3 show the Block Diagrams. Figures 6.4 to 6.6 show the Associated Registers. Table 6.1 VCC Monitor Specification of Voltage Detection Circuit Item Voltage to Monitor Detection Target Voltage Detection 1 Vdet1 Whether passing through Vdet1 by rising or falling None Voltage Detection 2 Vdet2 Whether passing through Vdet2 by rising or falling VCA13 bit in VCA1 register Whether VCC is higher or lower than Vdet2 Voltage Monitor 1 Reset Voltage Monitor 2 Reset Reset at Vdet1 > VCC; Reset at Vdet2 > VCC Restart CPU operation at Restart CPU operation VCC > Vdet1 after a specified time None Voltage Monitor 2 Interrupt Interrupt request at Vdet2 > VCC and VCC > Vdet2 when digital filter is enabled; Interrupt request at Vdet2 > VCC or VCC > Vdet2 when digital filter is disabled Available Available
Monitor
Process When Voltage Is Reset Detected
Interrupt
Digital Filter
Switch Enabled / Disabled Sampling Time
(Divide-by-n of fRING-S) (Divide-by-n of fRING-S) x4 x4 n : 1, 2, 4 and 8 n : 1, 2, 4 and 8
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6. Voltage Detection Circuit
VCC
VCA27
+
Internal Reference Voltage
Noise Filter
Vdet2
Voltage Detection 2 Signal VCA1 Register
b3
-
VCA26
VCA13 Bit
+ -
Voltage Detection 1 Signal
Vdet1
Figure 6.1
Block Diagram of Voltage Detection Circuit
Voltage Monitor 1 Reset Generation Circuit
VW1F1 to VW1F0 =00b =01b
Voltage Detection 1 Circuit
fRING-S VCA26
=10b
1/2
1/2
1/2
=11b
VCC
+ Voltage Detection 1 Signal Voltage detection 1 signal is held "H" when VCA26 bit is set to "0" (disabled)
Internal Reference Voltage
Digital Filter
VW1C1 VW1C0 VW1C6 VW1C7
Voltage Monitor 1 Reset Signal
VW1C0 to VW1C1, VW1F0 to VW1F1, VW1C6, VW1C7 : Bits in VW1C register VCA26: Bit in VCA2 register
Figure 6.2
Block Diagram of Voltage Monitor 1 Reset Generation Circuit
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6. Voltage Detection Circuit
Voltage Monitor 2 Interrupt / Reset Generation Circuit
VW2F1 to VW2F0 =00b =01b
Voltage Detection 2 Circuit
fRING-S VCA27 VCA13 VCC + Noise Filter Internal Reference voltage (Filter Width: 200ns) Voltage Detection 2 signal
=10b
1/2
1/2
1/2
=11b
VW2C2 bit is set to "0" (not detected) by writing "0" by program. When VCA27 bit is set to "0" (voltage detection 2 circuit disabled), VW2C2 bit is set to "0" Watchdog Timer Interrupt Signal Digital Filter VW2C2
Voltage detection 2 signal is held "H" when VCA27 bit is set to "0" (disabled) VW2C1
Voltage Monitor 2 Interrupt Signal
Non-Maskable Interrupt Signal
Oscillation Stop Detection Interrupt Signal Watchdog Timer Block VW2C3 VW2C7 VW2C0 VW2C6 Voltage Monitor 2 Reset Signal
Watchdog Timer Underflow Signal
This bit is set to "0" (not detected) by writing "0" by program.
VW2C0 to VW2C3, VW2F2, VW2F1, VW2C6, VW2C7: Bits in VW2C register VCA13: Bit in VCA1 register VCA27: Bit in VCA2 register
Figure 6.3
Block Diagram of Voltage Monitor 2 Interrupt / Reset Generation Circuit
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6. Voltage Detection Circuit
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0000
000
Symbol Address 0031h VCA1 Bit Symbol Bit Name -- Reserved Bit (b2-b0) VCA13 -- (b7-b4) Voltage Detection 2 Signal Monitor Flag(1) Reserved Bit
After Reset(2) 00001000b Function Set to "0" 0 : VCC < Vdet2 1 : VCC Vdet2 or voltage detection 2 circuit disabled Set to "0"
RW RW
RO
RW
NOTES : 1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to "1" (voltage detection 2 circuit enabled). The VCA13 bit is set to "1" (VCC Vdet 2) w hen the VCA27 bit in the VCA2 register is set to "0" (voltage detection 2 circuit disabled). 2. The softw are reset, w atchdog timer reset and voltage monitor 2 reset do not affect this register.
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
After Reset(4) Symbol VCA2 Address 0032h Hardw are Reset : 00h Pow er-On Reset, Voltage Monitor 1Reset : 01000000b Function Set to "0" 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW RW RW RW
000000
Bit Symbol Bit Name -- Reserved Bit (b5-b0) VCA26 VCA27 Voltage Detection 1 Enable Bit(2) Voltage Detection 2 Enable Bit(3)
NOTES : 1. Set the PRC3 bit in the PRCR register to "1" (w rite enable) before w riting to this register. 2. When using the voltage monitor 1 reset, set the VCA26 bit to "1". After the VCA26 bit is set from "0" to "1", the voltage detection circuit elapses for td(E-A) before starting operation. 3. When using the voltage monitor 2 interrupt / reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to "1". After the VCA27 bit is from "0" to "1", the voltage detection circuit elapses for td(E-A) before starting operation. 4. The softw are reset, w atchdog timer reset and voltage monitor 2 reset do not affect this register.
Figure 6.4
VCA1 and VCA2 Registers
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6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol VW1C
Address 0036h
After Reset(2) Hardw are Reset : 0000X000b Pow er-On Reset, Voltage Monitor 1 Reset : 0100X001b
Bit Symbol VW1C0
Bit Name Voltage Monitor 1 Reset Enable Bit(3) Voltage Monitor 1 Digital Filter Disable Mode Select Bit
Function 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) Set to "0". When read, its content is indeterminate.
b5 b4
RW RW
VW1C1
RW
VW1C2 -- (b3) VW1F0
Reserved Bit Reserved Bit Sampling Clock Select Bit
RW RO RW
VW1F1 Voltage Monitor 1 Circuit Mode Select Bit Voltage Monitor 1 Reset Generation Condition Select Bit
0 0 : fRING-S divide-by-1 0 1 : fRING-S divide-by-2 1 0 : fRING-S divide-by-4 1 1 : fRING-S divide-by-8 When the VW1C0 bit is set to "1" (enables voltage monitor 1 reset), set to "1". When the VW1C1 bit is set to "1" (digital filter disabled mode), set to "1".
RW
VW1C6
RW
VW1C7
RW
NOTES : 1. Set the PRC3 bit in the PRCR register to "1" (w rite enable) before w riting to this register. When rew riting the VW1C register, the VW1C2 bit may be set to "1". Set the VW1C2 bit to "0" after rew riting the VW1C register. 2. The value after reset remains unchanged in softw are reset, w atchdogi timer reset and voltage monitor 2 reset. 3. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to "1" (voltage detection 1 circuit enabled). Set the VW1C0 bit to "0" (disable), w hen the VCA26 bit is set to "0" (voltage detection 1 circuit disabled).
Figure 6.5
VW1C Register
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6. Voltage Detection Circuit
Voltage Monitor 2 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol VW2C Bit Symbol VW2C0
Address 0037h Bit Name Voltage Monitor 2 Interrupt / Reset Enable Bit(6, 10) Voltage Monitor 2 Digital Filter Disable Mode Select Bit(2)
After Reset(8) 00h Function 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) 0 : Not detected 1 : Vdet2 pass detected 0 : Not detected 1 : Detected
b5 b4
RW RW
VW2C1
RW
VW2C2 VW2C3 VW2F0
Voltage Change Detection Flag(3,4,8) WDT Detection Flag(4,8) Sampling Clock Select Bit
RW RW RW
VW2F1 VW2C6 Voltage Monitor 2 Circuit Mode Select Bit(5) Voltage Monitor 2 Interrupt / Reset Generation Condition Select Bit(7,9)
0 0 : fRING-S divide-by-1 0 1 : fRING-S divide-by-2 1 0 : fRING-S divide-by-4 1 1 : fRING-S divide-by-8 0 : Voltage monitor 2 interrupt mode 1 : Voltage monitor 2 reset mode 0 : When VCC reaches Vdet2 or above 1 : When VCC reaches Vdet2 or below
RW RW
VW2C7
RW
NOTES : 1. Set the PRC3 bit in the PRCR register to "1" (rew rite enable) before w riting to this register. When rew riting the VW2C register, the VW2C2 bit may be set to "1". Set the VW2C2 bit to "0" after rew riting the VW2C register. 2. When the voltage monitor 2 interrupt is used to exit stop mode and to return again, w rite "0" to the VW2C1 bit before w riting "1". 3. This bit is enabled w hen the VCA27 bit in the VCA2 register is set to "1" (voltage detection 2 circuit enabled). 4. Set this bit to "0" by a program. When w riting "0" by a program, it is set to "0" (It remains unchanged even if it is set to "1"). 5. This bit is enabled w hen the VW2C0 bit is set to "1" (voltage monitor 2 interrupt / enables reset). 6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to "1" (voltage detection 2 circuit enabled). Set the VW2C0 bit to "0" (disable) w hen the VCA27 bit is set to "0" (voltage detection 2 circuit disabled). 7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to "1" (digital filter disabled mode). 8. The VW2C2 and VW2C3 bits remain unchanged in the softw are reset, w atchdog timer reset and voltage monitor 2 reset. 9. When the VW2C6 bit is set to "1" (voltage monitor 2 reset mode), set the VW2C7 bit to "1" (w hen VCC reaches to Vdet2 or below )(do not set to "0"). 10. Set the VW2C0 bit to "0" (disabled) under the conditions of the VCA13 bit in the VCA1 register set to "1" (VCC Vdet2 or voltage detection 2 circuit disabled), the VW2C1 bit set to "1" (digital filter disabled mode) and the VW2C7 bit set to "0" (w hen VCC reaches Vdet2 or above). Set the VW2C0 bit to "0" (disabled) under the conditions of the VCA13 bit set to "0" (VCC < Vdet2), the VW2C1 bit set to "1" (digital filter disabled mode) and the VW2C7 bit set to "1" (w hen VCC reaches Vdet2 or below ).
Figure 6.6
VW2C Register
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6. Voltage Detection Circuit
6.1 6.1.1
Monitoring VCC Input Voltage Monitoring Vdet1
Vdet1 cannot be monitored.
6.1.2
Monitoring Vdet2
Set the VCA27 bit in the VCA2 register to "1" (voltage detection 2 circuit enabled). After td(E-A) (refer to 19. Electrical Characteristics) elapse, Vdet2 can be monitored by the VCA13 bit in the VCA1 register.
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6. Voltage Detection Circuit
6.2
Voltage Monitor 1 Reset
Table 6.2 lists the Setting Procedure of Voltage Monitor 1 Reset Associated Bit and Figure 6.7 shows the Operating Example of Voltage Monitor 1 Reset. When using the voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to "1" (digital filter disabled). Table 6.2 Procedure 1 2 3(1) Setting Procedure of Voltage Monitor 1 Reset Associated Bit When Using Digital Filter When Not Using Digital Filter Set the VCA26 bit in the VCA2 register to "1" (voltage detection 1 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Set the VW1C7 bit in the VW1C register to by the VW1F0 to VW1F1 bits in the VW1C "1" register Set the VW1C1 bit in the VW1C register to Set the VW1C1 bit in the VW1C register to "0" (digital f ilter enabled). "1" (digital filter disabled) Set the VW1C6 bit in the VW1C register to "1" (voltage monitor 1 reset mode) Set the VW1C2 bit in the VW1C register to "0" Set the CM14 bit in the CM1 register to "0" - (low-speed on-chip oscillator on) Wait for the sampling clock of the digital - (no wait time) filter x 4 cycles Set the VW1C0 bit in the VW1C register to "1" (enables voltage monitor 1 reset)
4(1) 5(1) 6 7 8 9
NOTES: 1. When the VW1C0 bit is set to "0" (disabled), procedures 3, 4 and 5 can be executed simultaneously (with 1 instruction).
VCC Vdet1 (Typ. 2.85V)
Sampling Clock of Digital Filter x 4 Cycles When the VW1C1 bit is set to "0" (digital filter enabled) Internal Reset Signal
1 x 32 fRING-S
1 x 32 fRING-S
When the VW1C1 bit is set to "1" (digital filter disabled) and the VW1C7 bit is set to "1"
Internal Reset Signal
VW1C1 and VW1C7 : Bits in VW1C Register The above applies to the following conditions. * VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled) * VW1C0 bit in VW1C register = 1 (enables voltage monitor 1 reset ) * VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode) When the internal reset signal is held "L", the pins, CPU and SFR are reset. The internal reset signal is changed from "L" to "H", the program is executed beginning with the address indicated by the reset vector. Refer to 4. Special Function Register (SFR) for the SFR status after reset.
Figure 6.7
Operating Example of Voltage Monitor 1 Reset
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6. Voltage Detection Circuit
6.3
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.3 lists the Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bit. Figure 6.8 shows the Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset. When using the voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to "1" (digital filter disabled). Table 6.3 Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bit When Using Digital Filter When Not Using Digital Filter Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Interrupt Reset Interrupt Reset Set the VCA27 bit in the VCA2 register to "1" (voltage detection 2 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Select the timing of the interrupt and reset by the VW2F0 to VW2F1 bits in the VW2C request by the VW2C7 bit in the VW2C register register(1) Set the VW2C1 bit in the VW2C register to Set the VW2C1 bit in the VW2C register to "0" (digital filter enabled) "1" (digital filter disabled) Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in the VW2C register to the VW2C register to the VW2C register to the VW2C register to "0" (voltage monitor 2 "1" (voltage monitor 2 "0" (voltage monitor 2 "1" (voltage monitor 2 reset mode) interrupt mode) reset mode) interrupt mode) Set the VW2C2 bit in the VW2C register to "0" (passing of Vdet2 is not detected) - Set the CM14 bit in the CM1 register to "0" (low-speed on-chip oscillator on) Wait for the sampling clock of the digital filter - (no wait time) x 4 cycles Set the VW2C0 bit in the VW2C register to "1" (enables voltage monitor 2 interrupt / reset)
Procedure 1 2 3(2)
4(2) 5(2)
6 7 8 9
NOTES: 1. Set the VW2C7 bit to "1" (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset. 2. When the VW2C0 bit is set to "0" (disabled), procedures 3, 4 and 5 can be executed simultaneously (with 1 instruction).
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6. Voltage Detection Circuit
Vdet2 (Typ. 3.30V)
VCC
2.7V(1)
"1" VCA13 Bit "0" Sampling Clock of Digital Filter x 4 Cycles "1" VW2C2 Bit "0" Set to "0" by a program When the VW2C1 bit is set to "0" (digital filter enabled) Set to "0" by interrupt request acknowledgement Sampling Clock of Digital Filter x 4 Cycles
Voltage Monitor 2 Interrupt Request (VW2C6=0) Internal Reset Signal (VW2C6=1)
Set to "0" by a program "1" When the VW2C1 bit is set to "1" (digital filter disabled) and the VW2C7 bit is set to "0" (Vdet2 or above) VW2C2 Bit "0" Voltage Monitor 2 Interrupt Request (VW2C6=0) Set to "0" by interrupt request acknowledgement
Set to "0" by a program "1" VW2C2 Bit "0" When the VW2C1 bit is set to "1" (digital filter disabled) and the VW2C7 bit is set to "1" (Vdet2 or below) Voltage Monitor 2 Interrupt Request (VW2C6=0) Internal Reset Signal (VW2C6=1) Set to "0" by interrupt request acknowledgement
VCA13 : Bit in VCA1 Register VW2C1, VW2C2, VW2C6, VW2C7 : Bit in VW2C Register The above applies to the following conditions. * VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled) * VW2C0 bit in VW2C register = 1 (enables voltage monitor 2 interrupt and voltage monitor 2 reset) NOTES: 1. When the voltage monitor 1 reset is not used, set the power supply to VCC 2.7.
Figure 6.8
Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
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7. Processor Mode
7.
7.1
Processor Mode
Types of Processor Mode
Single-chip mode can be selected as processor mode. Table 7.1 lists Features of Processor Mode. Figure 7.1 shows the PM0 Register and Figure 7.2 shows the PM1 Register. Table 7.1 Features of Processor Mode Pins to which I/O ports are assigned SFR, Internal RAM, Internal ROM All pins are I/O ports or peripheral function I/O pins Access Area
Processor Mode Single-Chip Mode
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol PM0
Address 0004h
After Reset 00h Function Set to "0" The microcomputer is reset w hen this bit is set to "1". When read, its content is "0". RW RW RW
Bit Symbol Bit Name -- Reserved Bit (b2-b0) Softw are Reset Bit PM03
-- (b7-b4)
Nothing is assigned. When w rite, set to "0". When read, its content is "0".
--
NOTES : 1. Set the PRC1 bit in the PRCR register to "1" (w rite enable) before rew riting to this register.
Figure 7.1
PM0 Register
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Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol PM1
Address 0005h
After Reset 00h Function RW -- RW RW -- RW
Bit Symbol Bit Name Nothing is assigned. When w rite, set to "0". -- When read, its content is indeterminate. (b0) -- (b1) PM12 -- (b6-b3) -- (b7) Reserved Bit WDT Interrupt/Reset Sw itch Bit Set to "0"
0 : Watchdog Timer Interrupt 1 : Watchdog Timer Reset(2)
Nothing is assigned. When w rite, set to "0". When read, its content is "0". Reserved Bit Set to "0"
NOTES : 1. Set the PRC1 bit in the PRCR register to "1" (w rite enable) before rew riting to this register. 2. The PM12 bit is set to "1" by a program (It remains unchanged even if it is set to "0"). When the CSPRO bit in the CSPR register is set to "1" (selects count source protect mode), the PM12 bit is automatically set to "1".
Figure 7.2
PM1 Register
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8. Bus
8.
Bus
During access, the ROM/RAM and SFR vary from bus cycles. Table 8.1 lists Bus Cycles for Access Space of the R8C/14 Group and Table 8.2 lists Bus Cycles for Access Space of the R8C/15 Group. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits) unit, these area are accessed twice in 8-bit unit. Table 8.3 lists Access Unit and Bus Operation. Table 8.1 Bus Cycles for Access Space of the R8C/14 Group Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock
Access Area SFR ROM/RAM Table 8.2
Bus Cycles for Access Space of the R8C/15 Group Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock
Access Area SFR/Data flash Program ROM/RAM Table 8.3
Area Even Address Byte Access
Access Unit and Bus Operation
SFR, Data flash CPU Clock Address Data Even Data ROM (Program ROM), RAM CPU Clock Address Data CPU Clock Odd Data Address Data CPU Clock Even Data Even+1 Data Address Data CPU Clock Odd Data Odd+1 Data Address Data Odd Data Odd+1 Data Even Data Even+1 Data Odd Data Even Data
Odd Address Byte Access
CPU Clock Address Data
Even Address Word Access
CPU Clock Address Data
Odd Address Word Access
CPU Clock Address Data
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9. Clock Generation Circuit
9.
Clock Generation Circuit
The MCU has two on-chip clock generation circuits: * Main clock oscillation circuit * On-chip oscillator (oscillation stop detection function) Table 9.1 lists Specification of Clock Generation Circuit. Figure 9.1 shows a Clock Generation Circuit. Figures 9.2 to 9.5 show clock-associated registers. Table 9.1 Item Use of Clock Specification of Clock Generation Circuit Main Clock Oscillation Circuit * CPU clock source * Peripheral function clock source On-Chip Oscillator High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator * CPU clock source * CPU clock source * Peripheral function clock * Peripheral function clock source source * CPU and peripheral function * CPU and peripheral function clock sources when main clock sources when main clock stops oscillating clock stops oscillating Approx. 8MHz Approx. 125kHz - -
Clock Frequency 0 to 20MHz Connectable * Ceramic resonator Oscillator * Crystal oscillator Oscillator XIN, XOUT(1) Connect Pins Oscillation Stop, Usable Restart Function Oscillator Status Stop After Reset Others Externally generated clock can be input
(Note 1) Usable Stop -
(Note 1) Usable Oscillate -
NOTES: 1. This pin can be used as P4_6 and P4_7 when using the on-chip oscillator clock for a CPU clock while the main clock oscillation circuit is not used.
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9. Clock Generation Circuit
HRA1 Register Frequency Adjustable HRA00
HRA2 Register On-Chip Oscillator Clock
High-Speed On-Chip Oscillator HRA01=1 HRA01=0 Low-Speed On-Chip Oscillator
fRING-fast Watchdog Timer fRING fRING128 SSU
1/128
Power-On Reset Circuit Voltage Detection Circuit b f1 c f2 d e f4 f8 g
Timer C
INT0
Timer X
Timer Z
A/D Converter
UART0
CM14
fRING-S
CM10=1(Stop Mode) RESET Power-on reset Software reset Interrupt request WAIT Instruction CM13
SQ R
Oscillation Stop Detection Main Clock
SQ R
OCD2=1
f32 h
a XIN XOUT OCD2=0
Divider
CPU Clock
CM13 CM05 System Clock
CM02
b a 1/2
c 1/2
d 1/2
e 1/2 1/2
g
CM06=0 CM17 to CM16=11b CM06=1
CM02, CM05, CM06: Bits in CM0 register CM10, CM13, CM14, CM16, CM17: Bits in CM1 register OCD0, OCD1, OCD2: Bits in OCD register HRA00, HRA01: Bits in HRA0 register
CM06=0 CM17 to CM16=10b CM06=0 CM17 to CM16=01b CM06=0 CM17 to CM16=00b
h
Details of Divider Oscillation Stop Detection Circuit
Forcible discharge when OCD0(1)=0
Main Clock
Pulse generation circuit for clock edge detection and charge, discharge control circuit
Charge, Discharge Circuit OCD1(1)
Oscillation Stop Detection Interrupt Generation Circuit Detection Watchdog Timer Interrupt Voltage Watch 2 Interrupt OCD2 Bit Switch Signal
Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 2 Interrupt
NOTES : 1. Set the same value to the OCD1 and OCD0 bits.
CM14 Bit Switch Signal
Figure 9.1
Clock Generation Circuit
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9. Clock Generation Circuit
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
00
Symbol Address 0006h CM0 Bit Symbol Bit Name -- Reserved Bit (b1-b0) WAIT Peripheral Function Clock Stop Bit
After Reset 68h Function Set to "0" 0 : Peripheral function clock does not stop in w ait mode 1 : Peripheral function clock stops in w ait mode Set to "1" Set to "0" 0 : Main clock oscillates 1 : Main clock stops (3) 0 : Enables CM16, CM17 1 : Divide-by-8 mode Set to "0"
RW RW
CM02
RW
-- (b3) -- (b4) CM05 CM06 -- (b7)
Reserved Bit Reserved Bit Main Clock (XIN-XOUT) Stop Bit(2,4) System Clock Division Select Bit 0(5) Reserved Bit
RW RW RW RW RW
NOTES : 1. Set the PRC0 bit in the PRCR register to "1" (w rite enable) before rew riting to this register. 2. The CM05 bit is to stop the main clock w hen the on-chip oscillator mode is selected. Do not use this bit for w hether the main clock is stopped. To stop the main clock, set the bits in the follow ing orders: (a) Set the OCD1 to OCD0 bits in the OCD register to "00b" (oscillation stop detection function disabled). (b) Set the OCD2 bit to "1" (selects on-chip oscillator clock). 3. Set the CM05 bit to "1" (main clock stops) and the CM13 bit in the CM1 register to "1" (XIN-XOUT pin) w hen the external clock is input. 4. When the CM05 bit is set to "1" (stops main clock), P4_6 and P4_7 can be used as input ports. 5. When entering stop mode from high or middle speed mode, the CM06 bit is set to "1" (divide-by-8 mode).
Figure 9.2
CM0 Register
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9. Clock Generation Circuit
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol CM1 Bit Symbol CM10 -- (b1) -- (b2) CM13 CM14 CM15
Address 0007h Bit Name All Clock Stop Control Bit(4,7,8) Reserved Bit Reserved Bit Port XIN-XOUT Sw itch Bit(7)
After Reset 20h Function 0 : Oscillates clock 1 : Stops all Clocks (stop mode) Set to "0" Set to "0" 0 : Input port P4_6, P4_7 1 : XIN-XOUT Pin
RW RW RW RW RW RW RW
Low -Speed On-Chip Oscillation Stop 0 : Low -speed on-chip oscillator on Bit(5,6,8) 1 : Low -speed on-chip oscillator off XIN-XOUT Drive Capacity Select Bit(2) 0 : LOW 1 : HIGH System Clock Division Select Bit 1(3) b7 b6 0 0 : No division mode 0 1 : Divide-by-2 mode 1 0 : Divide-by-4 mode 1 1 : Divide-by-16 mode
CM16
RW
CM17
RW
NOTES : 1. Set the PRC0 bit in the PRCR register to "1" (w rite enable) before rew riting to this register. 2. When entering stop mode from high or middle speed mode, this bit is set to "1" (drive capacity HIGH). 3. When the CM06 bit is set to "0" (CM16, CM17 bits enabled), this bit becomes enabled. 4. If the CM10 bit is "1" (stop mode), the internal feedback resistor becomes disabled. 5. When the OCD2 bit is set to "0" (selects main clock), the CM14 bit is set to "1" (stops low -speed on-chip oscillator). When the OCD2 bit is set to "1" (selects on-chip oscillator clock), the CM14 bit is set to "0" (low -speed on-chip oscillator on). It remains unchanged even if it is set to "1". 6. When using the voltage detection interrupt, CM14 bit is set to "0" (low -speed on-chip oscillator on). 7. When the CM10 bit is set to "1" (stop mode) or the CM05 bit in the CM0 register to "1" (main clock stops) and the CM13 bit is set to "1" (XIN-XOUT pin), the XOUT (P4_7) pin becomes "H". When the CM13 bit is set to "0" (input ports, P4_6, P4_7), the P4_7 (XOUT) enters input mode. 8. In count source protect mode (Refer to 12.2 Count Source Protect Mode), the value remains unchanged even if the CM10 and CM14 bits are set.
Figure 9.3
CM1 Register
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9. Clock Generation Circuit
Oscillation Stop Detection Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol OCD Bit Symbol OCD0
Address 000Ch Bit Name Oscillation Stop Detection Enable Bit
After Reset 04h Function
b1 b0
RW RW
OCD1
0 0 : Oscillation stop detection function disabled 0 1 : Do not set 1 0 : Do not set 1 1 : Oscillation stop detection function enabled(4,7) 0 : Selects main clock(7) 1 : Selects on-chip oscillator clock(2) 0 : Main clock oscillates 1 : Main clock stops Set to "0"
RW
System Clock Select Bit(6) OCD2 OCD3 -- (b7-b4) Clock Monitor Bit(3,5) Reserved Bit
RW RO RW
NOTES : 1. Set the PRC0 bit in the PRCR register to "1" (w rite enable) before rew riting to this register. 2. The OCD2 bit is automatically set to "1" (selects on-chip oscillator clock) if a main clock oscillation stop is detected w hile the OCD1 to OCD0 bits are set to "11b" (oscillation stop detection function enabled). If the OCD3 bit is set to "1" (main clock stops), the OCD2 bit remains unchanged w hen w riting "0" (selects main clock). 3. The OCD3 bit is enabled w hen the OCD1 to OCD0 bits are set to "11b". 4. Set the OCD1 to OCD0 bits to "00b" (oscillation stop detection function disabled) before entering stop and on-chip oscillator mode (main clock stops). 5. The OCD3 bit remains "0" (main clock oscillates) if the OCD1 to OCD0 bits are set to "00b". 6. The CM14 bit is set to "0" (low -speed on-chip oscillator on) if the OCD2 bit is set to "1" (selects on-chip oscillator clock). 7. Refer to Figure 9.9 Procedure of Sw itching Clock Source From Low -Speed On-Chip Oscillator to Main Clock for the sw itching procedure w hen the main clock re-oscillates after detecting an oscillation stop.
Figure 9.4
OCD Register
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9. Clock Generation Circuit
High-speed On-Chip Oscillator Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol HRA0 Bit Symbol HRA00 HRA01 -- (b7-b2)
Address 0020h Bit Name High-Speed On-Chip Oscillator Enable Bit
After Reset 00h Function 0 : High-speed on-chip oscillator off 1 : High-speed on-chip oscillator on
RW RW RW RW
High-speed On-Chip Oscillator Select 0 : Selects low -speed on-chip oscillator (3) 1 : Selects high-speed on-chip oscillator Bit(2) Reserved Bit Set to "0"
NOTES : 1. Set the PRC0 bit in the PRCR register to "1" (w rite enable) before rew riting to this register. 2. Change the HRA01 bit under the follow ing conditions. * HRA00 = 1 (high-speed on-chip oscillation) * The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on) 3. When setting the HRA01 bit to "0" (selects low -speed on-chip oscillator), do not set the HRA00 bit to "0" (high-speed on-chip oscillator off) at the same time. Set the HRA00 bit to "0" after setting the HRA01 bit to "0".
Figure 9.5
HRA0 Register
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9. Clock Generation Circuit
High-speed On-Chip Oscillator Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol HRA1
Address 0021h
After Reset When Shipping RW
Function The frequency of high-speed on-chip oscillator is adjusted w ith bits 0 to 7. High-speed on-chip oscillator frequency = 8MHz (HRA1 register = value w hen shipping ; fRING-fast mode 0) Set the value of the HRA1 register to smaller (minimum value : 00h), the frequency w ill be higher Set the value of the HRA1 register to larger (maximum value : FFh), the frequecny w ill be low er NOTES : 1. Set the PRC0 bit in the PRCR register to "1" (w rite enable) before rew riting to this register.
RW
High-Speed On-Chip Oscillator Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol HRA2 Bit Symbol HRA20
HRA21 -- (b4-b2) -- (b7-b5)
Address After Reset 0022h 00h Bit Name Function High-Speed On-Chip Oscillator Mode b1 b0 0 0 : fRING-fast mode 0(2) Select Bit 0 1 : fRING-fast mode 1(3) 1 0 : fRING-fast mode 2(4) 1 1 : Do not set Reserved Bit Set to "0"
RW RW
RW RW --
Nothing is assigned. When w rite, set to "0". When read, its content is "0".
NOTES : 1. Set the PRC0 bit in the PRCR register to "1" (w rite enable) before rew riting to this register. 2. High-speed on-chip oscillator frequency = 8MHz (HRA1 register = value w hen shipping) 3. If fRING-fast mode 0 is sw itched to fRING-fast mode 1, frequency w ill increase 1.5 times. 4. If fRING-fast mode 0 is sw itched to fRING-fast mode 2, frequency w ill increase 0.5 times.
Figure 9.6
HRA1 and HRA2 Registers
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R8C/14 Group, R8C/15 Group The following describes the clocks generated by the clock generation circuit.
9. Clock Generation Circuit
9.1
Main Clock
This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillation circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillation circuit contains a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the chip. The main clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 9.7 shows the Examples of Main Clock Connection Circuit. During reset and after reset, the main clock stops. The main clock starts oscillating when the CM05 bit in the CM0 register is set to "0" (main clock on) after setting the CM13 bit in the CM1 register to "1" (XIN- XOUT pin). To use the main clock for the CPU clock source, set the OCD2 bit in the OCD register to "0" (select main clock) after the main clock is oscillating stably. The power consumption can be reduced by setting the CM05 bit in the CM0 register to "1" (stop main clock) if the OCD2 bit is set to "1" (select on-chip oscillator clock). When the clocks externally generated to the XIN pin are input, a main clock does not stop if setting the CM05 bit to "1". If necessary, use an external circuit to stop the clock. In stop mode, all clocks including the main clock stop. Refer to 9.4 Power Control for details.
Microcomputer (Built-In Feedback Resistor) XIN XOUT Rd(1)
Microcomputer (Built-In Feedback Resistor) XIN XOUT Open Externally Derived Clock
CIN
COUT
VCC VSS
Ceramic Resonator External Circuit
External Clock Input Clock
NOTES : 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction.
Figure 9.7
Examples of Main Clock Connection Circuit
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9. Clock Generation Circuit
9.2
On-Chip Oscillator Clock
This clock is supplied by an on-chip oscillator. The on-chip oscillator contains a high-speed on-chip oscillator and a low-speed on-chip oscillator. Either an on-chip oscillator clock is selected by the HRA01 bit in the HRA0 register.
9.2.1
Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fRING, fRING128 and fRING-S. After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator by divide-by-8 is selected for the CPU clock. If the main clock stops oscillating when the OCD1 to OCD0 bits in the OCD register are set to "11b" (oscillation stop detection function enabled), the low-speed on-chip oscillator automatically starts operating, supplying the necessary clock for the microcomputer. The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating ambient temperature. The application products must be designed with sufficient margin for the frequency change.
9.2.2
High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fRING, fRING128, and fRING1-fast. After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. The oscillation starts by setting the HRA00 bit in the HRA0 register to "1" (high-speed on-chip oscillator on). The frequency can be adjusted by the HRA1 and HRA2 registers. Since the difference in delay between the bits, adjust by changing each bit.
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9. Clock Generation Circuit
9.3
CPU Clock and Peripheral Function Clock
There are two type clocks: a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 9.1 Clock Generation Circuit.
9.3.1
System Clock
The system clock is a clock source for the CPU and peripheral function clocks. The main clock or onchip oscillator clock can be selected.
9.3.2
CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer. The system clock can be the divide-by-1 (no division), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register to select the value of the division. After reset, the low-speed on-chip oscillator clock divided-by-8 provides the CPU clock. When entering stop mode from high-speed or medium-speed mode, the CM06 bit is set to "1" (divide-by-8 mode).
9.3.3
Peripheral Function Clock (f1, f2, f4, f8, f32)
The peripheral function clock is operating clock for the peripheral functions. The clock fi (i=1, 2, 4, 8, 32) is generated by the system clock divided-by-i. The clock fi is used for timers X, Y, Z, C, serial interface and A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to "1" (peripheral function clock stops in wait mode), the clock fi stops.
9.3.4
fRING and fRING128
fRING and fRING128 are operating clocks for the peripheral functions. The fRING runs at the same frequency as the on-chip oscillator clock and can be used as the source for the timer X. The fRING128 is generated by the fRING by dividing it by 128 and can be used for the timer C. When the WAIT instruction is executed, the clocks fRING and fRING128 do not stop.
9.3.5
fRING-fast
fRING-fast is used as the count source for the timer C. The fRING-fast is generated by the highspeed on-chip oscillator and provided by setting the HRA00 bit to "1". When the WAIT instruction is executed, the clock fRING-fast does not stop.
9.3.6
fRING-S
fRING-S is an operating clock for the watchdog timer and voltage detection circuit. When setting the CM14 bit to "0" (low-speed on-chip oscillator on) using the clock generated by the low-speed on-chip oscillator, the fRING-S can be provided. When the WAIT instruction is executed or in count source protect mode of the watchdog timer, fRING-S does not stop.
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9. Clock Generation Circuit
9.4
Power Control
There are three power control modes. All modes other than wait and stop modes are referred to as normal operating mode.
9.4.1
Normal Operating Mode
Normal operating mode is further separated into four modes. In normal operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source after switching needs to be stabilized and oscillated. If the new clock source is the main clock, allow sufficient wait time in a program until an oscillation is stabilized before exiting. Table 9.2 Setting and Mode of Clock Associated Bit Modes High-Speed Mode divide-by-2 MediumSpeed divide-by-4 Mode divide-by-8 divide-by-16 High-Speed, no division Low-Speed divide-by-2 On-Chip divide-by-4 Oscillator divide-by-8 Mode(1) divide-by-16 OCD Register OCD2 0 0 0 0 0 1 1 1 1 1 CM1 Register CM17, CM16 CM13 00b 1 01b 1 10b 1 - 1 11b 1 00b - 01b - 10b - - - 11b - CM0 Register CM06 CM05 0 0 0 0 0 0 1 0 0 0 0 - 0 - 0 - 1 - 0 -
NOTES: 1. The low-speed on-chip oscillator is used as the on-chip oscillator clock when the CM14 bit in the CM1 register is set to "0" (low-speed on-chip oscillator on) and the HRA01 bit in the HRA0 register is set to "0". The high-speed on-chip oscillator is used as the on-chip oscillator clock when the HRA00 bit in the HRA0 register is set to "1" (high-speed on-chip oscillator A on) and the HRA01 bit in the HRA0 register is set to "1".
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9.4.1.1
High-Speed Mode
The main clock divided-by-1 (no division) provides the CPU clock. If the CM14 bit is set to "0" (lowspeed on-chip oscillator on) or the HRA00 bit in the HRA0 register is set to "1" (high-speed on-chip oscillator on), the fRING and fRING128 can be used for timers X and C. When the HRA00 bit is set to "1", fRING-fast can be used for timer C. When the CM14 bit is set to "0" (low-speed on-chip oscillator on), fRING-S can be used for the watchdog timer and voltage detection circuit.
9.4.1.2
Medium-Speed Mode
The main clock divided-by-2, -4, -8 or -16 provides the CPU clock. If the CM14 bit is set to "0" (lowspeed on-chip oscillator on) or the HRA00 bit in the HRA0 register is set to "1" (high-speed on-chip oscillator on), the fRING and fRING128 can be used for timers X and C. When the HRA00 bit is set to "1", fRING-fast can be used for timer C. When the CM14 bit is set to "0" (low-speed on-chip oscillator on), fRING-S can be used for the watchdog timer and voltage detection circuit.
9.4.1.3
High-Speed, Low-Speed On-Chip Oscillator Mode
The on-chip oscillator clock divided-by-1 (no division), -2, -4, -8 or -16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. When the HRA00 bit is set to "1", fRING-fast can be used for timer C. When the CM14 bit is set to "0" (low-speed onchip oscillator on), fRING-S can be used for the watchdog timer and voltage detection circuit.
9.4.2
Wait Mode
Since the CPU clock stops in wait mode, the CPU operated in the CPU clock and the watchdog timer when count source protection mode is disabled stops. The main clock and on-chip oscillator clock do not stop and the peripheral functions using these clocks maintain operating.
9.4.2.1
Peripheral Function Clock Stop Function
If the CM02 bit is set to "1" (peripheral function clock stops in wait mode), the f1, f2, f4, f8 and f32 clocks stop in wait mode. The power consumption can be reduced.
9.4.2.2
Entering Wait Mode
The microcomputer enters wait mode by executing the WAIT instruction.
9.4.2.3
Pin Status in Wait Mode
The status before entering wait mode is maintained.
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9.4.2.4
Exiting Wait Mode
The microcomputer exits wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "000b" (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to "0" (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to "1" (peripheral function clock stops in wait mode), the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals can be used to exit wait mode. Table 9.3 lists Interrupts to Exit Wait Mode and Usage Conditions. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority level to the ILVL2 to ILVL0 bits in the interrupt control register of the peripheral function interrupts to use for exiting wait mode. Set the ILVL2 to ILVL0 bits of the peripheral function interrupts not to use for exiting wait mode to "000b" (disables interrupt). (2) Set the I flag to "1". (3) Operate the peripheral function to use for exiting wait mode. When an interrupt request is generated and the CPU clock supply is started if exiting by the peripheral function interrupt, an interrupt sequence is executed. The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock when the WAIT instruction is executed. Table 9.3 Interrupts to Exit Wait Mode and Usage Conditions CM02=0 Usable when operating with internal or external clock Usable in all modes Usable Usable in one-shot mode Usable in all modes Usable in all modes Usable in all modes Usable CM02=1 Usable when operating with external clock -(Do not use) Usable -(Do not use) Usable in event counter mode -(Do not use) -(Do not use) Usable (INT0 and INT3 can be used if there is no filter. Usable -(Do not use) Usable in count source protect mode
Interrupt Serial Interface Interrupt SSU Interrupt Key Input Interrupt A/D Conversion Interrupt Timer X Interrupt Timer Z Interrupt Timer C Interrupt INT Interrupt
Voltage Monitor 2 Interrupt Usable Oscillation Stop Detection Usable Interrupt Watchdog Timer Interrupt Usable in count source protect mode
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9. Clock Generation Circuit
9.4.3
Stop Mode
Since the oscillator circuits stop in wait mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions clocked by these clocks stop operating. The least power required to operate the microcomputer is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the internal RAM is maintained. The peripheral functions clocked by external signals maintain operating. Table 9.4 lists Interrupts to Exit Stop Mode and Usage Conditions. Table 9.4 Interrupts to Exit Stop Mode and Usage Conditions Usage Conditions - INT0 can be used if there is no filter No filter. Interrupt request is generated at INT3 input. (TCC06 bit in TCC0 register is set to "1") When external pulse is counted in event counter mode When external clock is selected Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to "1")
Interrupt Key Input Interrupt INT0 to INT1 Interrupts INT3 Interrupt Timer X Interrupt Serial Interface Interrupt Voltage Monitor 2 Interrupt
9.4.3.1
Entering Stop Mode
The microcomputer enters stop mode by setting the CM10 bit in the CM1 register to "1" (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to "1" (divide-by-8 mode) and the CM15 bit in the CM10 register is set to "1" (drive capability HIGH of main clock oscillator circuit). When using stop mode, set the OCD1 to OCD0 bits to "00b" (oscillation stop detection function disabled) before entering stop mode.
9.4.3.2
Pin Status in Stop Mode
The status before entering wait mode is maintained. However, when the CM13 bit in the CM1 register is set to "1" (XIN-XOUT pins), the XOUT(P4_7) pin is held "H". When the CM13 bit is set to "0" (input port P4_6 and P4_7), the P4_7(XOUT) is held in input status.
9.4.3.3
Exiting Stop Mode
The microcomputer exits stop mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit stop mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "000b" (disables interrupts) before setting the CM10 bit to "1". When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to "1". (1) Set the interrupt priority level to the ILVL2 to ILVL0 bits of the peripheral function interrupts to use for exiting stop mode. Set the ILVL2 to ILVL0 bits of the peripheral function interrupts not to use for exiting stop mode to "000b" (disables interrupt). (2) Set the I flag to "1". (3) Operates the peripheral function to use for exiting stop mode. When an interrupt request is generated and the CPU clock supply is started if exiting by the peripheral function interrupt, an interrupt sequence is executed. The CPU clock, when exiting stop mode by a peripheral function interrupt, is the divide-by-8 of the clock which is used before entering stop mode.
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R8C/14 Group, R8C/15 Group Figure 9.8 shows the State Transition of Power Control.
9. Clock Generation Circuit
Reset
CM OC 1 4 D 2 = 0, = 1 HR A
01
Low-speed On-chip Oscillator Mode OCD2=1 HRA01=0 CM14=0
0,
=0
,
High-speed On-chip Oscillator Mode OCD2=1 HRA01=1 HRA00=1
HRA00=1, HRA01=1
CM14=1, HRA01=0
High-speed Mode, Middle-speed Mode OCD2=0 CM05=0 CM13=1
There are six power control modes. (1) High-speed mode (2) Middle-speed mode (3) High-speed on-chip oscillator mode (4) Low-speed on-chip oscillator mode (5) Wait mode (6) Stop mode
CM OC 1 3 D 2 =1 , =0 C M 0
5=
1, 0= A0 = 1 H R D2 OC HR A0 1= 1, M
,C =1 13 =0 CM D2 OC
Interrupt
WAIT Instruction
Wait Mode
05 =0 ,
CM05: Bit in CM0 register CM10, CM13, CM14: Bit in CM1 register OCD2: Bit in OCD register HRA00, HRA01: Bit in HRA0 register
Interrupt
CM10=1 (All oscillators stop)
Stop Mode
Figure 9.8
State Transition of Power Control
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9. Clock Generation Circuit
9.5
Oscillation Stop Detection Function
The oscillation stop detection function is a function to detect the stop of the main clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD register. Table 9.5 lists the Specification of Oscillation Stop Detection Function. When the main clock is the CPU clock source and the OCD1 to OCD0 bits are set to "11b" (oscillation stop detection function enabled), the system is placed in the following state if the main clock stops. * OCD2 bit in OCD register = 1 (on-chip oscillator clock selected) * OCD3 bit in OCD register = 1 (main clock stops) * CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates) * Oscillation stop detection interrupt request is generated Table 9.5 Specification of Oscillation Stop Detection Function Specification f(XIN) 2 MHz Set OCD1 to OCD0 bits to "11b" (oscillation stop detection function enabled) Oscillation stop detection interrupt is generated
Item Oscillation Stop Detection Enable Clock and Frequency Bandwidth Enabled Condition for Oscillation Stop Detection Function Operation at Oscillation Stop Detection
9.5.1
How to Use Oscillation Stop Detection Function
* The oscillation stop detection interrupt shares the vector with the voltage monitor 2 interrupt and
the watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt cause needs to be determined. Table 9.6 lists the Determine Interrupt Factor of Oscillation Stop Detection, Watchdog Timer and Voltage Monitor 2 Interrupts. When the main clock is re-oscillated after oscillation stop, switch the main clock to the clock source of the CPU clock and peripheral functions by a program. Figure 9.9 shows the Procedure of Switching Clock Source From Low-Speed On-Chip Oscillator to Main Clock. To enter wait mode while using the oscillation stop detection function, set the CM02 bit to "0" (peripheral function clock does not stop in wait mode). Since the oscillation stop detection function is a function preparing to stop the main clock by the external cause, set the OCD1 to OCD0 bits to "00b" (oscillation stop detection function disabled) when the main clock stops or oscillates in the program, that is stop mode is selected or the CM05 bit is changed. This function cannot be used when the main clock frequency is below 2 MHz. Set the OCD1 to OCD0 bits to "00b" (oscillation stop detection function disabled). When using the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the HRA01 bit in the HRA0 register to "0" (low-speed on-chip oscillator selected) and the OCD1 to OCD0 bits to "11b" (oscillation stop detection function enabled). When using the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the HRA01 bit to "1" (high-speed onchip oscillator selected) and the OCD1 to OCD0 bits to "11b" (oscillation stop detection function enabled).
* * * *
* *
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9. Clock Generation Circuit
Table 9.6
Determine Interrupt Factor of Oscillation Stop Detection, Watchdog Timer and Voltage Monitor 2 Interrupts
Generated Interrupt Cause Bit Showing Interrupt Cause Oscillation Stop Detection (a) OCD3 bit in OCD register = 1 ( (a) or (b) ) (b) OCD1 to OCD0 bits in OCD register = 11b and the OCD2 bit = 1 Watchdog Timer VW2C3 bit in VW2C register = 1 Voltage Monitor 2 VW2C2 bit in VW2C register = 1
Switch to Main clock
Determine OCD3 Bit 1(Main Clock Stop) 0(Main Clock oscillate)
Judge several times
Determine several times that the main clock is supplied Set OCD1 to OCD0 bits to "00b" (oscillation stop detection function disabled)
Set OCD2 bit to "0" (select Main Clock)
End OCD3 to OCD0 bits: Bits in OCD register
Figure 9.9
Procedure of Switching Clock Source From Low-Speed On-Chip Oscillator to Main Clock
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10. Protection
10. Protection
Protection function protects important registers from being easily overwritten when a program runs out of control. Figure 10.1 shows the PRCR Register. The following lists the registers protected by the PRCR register. * Registers protected by PRC0 bit : CM0, CM1, and OCD, HRA0, HRA1, HRA2 registers * Registers protected by PRC1 bit : PM0 and PM1 registers * Registers protected by PRC3 bit : VCA2, VW1C and VW2C registers
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol PRCR Bit Symbol
Address 000Ah Bit Name Protect Bit 0
PRC0
After Reset 00h Function Writing to the CM0, CM, OCD, HRA0, HRA1 and HRA2 registers is enabled. 0 : Disables w riting 1 : Enables w riting Writing to the PM0 and PM1 registers is enabled. 0 : Disables w riting 1 : Enables w riting Set to "0" Writing to the VCA2, VW1C and VW2C registers is enabled. 0 : Disables w riting 1 : Enables w riting Set to "0" When read, its content is "0".
RW
RW
Protect Bit 1 PRC1
RW
-- (b2)
Reserved Bit Protect Bit 3
RW
PRC3
RW
-- (b5-b4) -- (b7-b6)
Reserved Bit Reserved Bit
RW RO
Figure 10.1
PRCR Register
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11. Interrupt
11. Interrupt
11.1 11.1.1 Interrupt Overview Types of Interrupts
Figure 11.1 shows types of Interrupts.
Software (Non-Maskable Interrupt)
Undefined Instruction (UND Instruction) Overflow (INTO Instruction) BRK Instruction INT Instruction
Interrupt Special (Non-Maskable Interrupt) Hardware Peripheral Function(1) (Maskable Interrupt)
Watchdog Timer Oscillation Stop Detection Voltage Monitor 2 Single Step(2) Address Match
NOTES : 1. Peripheral function interrupts in the microcomputer are used to generate the peripheral interrupt. 2. Do not use this interrupt. For development tools only.
Figure 11.1
Interrupts
* Maskable Interrupt:
* Non-Maskable Interrupt:
The interrupt enable flag (I flag) enables or disables an interrupt. The interrupt priority order based on the interrupt priority level can be changed. The interrupt enable flag (I flag) does not enable or disable an interrupt. The interrupt priority order based on interrupt priority level cannot be changed.
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11. Interrupt
11.1.2
Software Interrupts
A software interrupt is generated when an instruction is executed. The software interrupts are nonmaskable interrupts.
11.1.2.1
Undefined Instruction Interrupt
The undefined instruction interrupt is generated when the UND instruction is executed.
11.1.2.2
Overflow Interrupt
The overflow interrupt is generated when the O flag is set to "1" (arithmetic operation overflow) and the INTO instruction is executed. Instructions to set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
11.1.2.3
BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
11.1.2.4
INT Instruction Interrupt
An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 4 to 31 are assigned to the peripheral function interrupt. Therefore, the microcomputer executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt is generated. In software interrupt numbers 0 to 31, the U flag is saved to the stack during instruction execution and set the U flag to "0" (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
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11. Interrupt
11.1.3
Special Interrupts
Special interrupts are non-maskable interrupts.
11.1.3.1
Watchdog Timer Interrupt
The watchdog timer interrupt is generated by the watchdog timer. Reset the watchdog timer after the watchdog timer interrupt is generated. For details, refer to 12. Watchdog Timer.
11.1.3.2
Oscillation Stop Detection Interrupt
Oscillation Stop Detection Interrupt is generated by the oscillation stop detection function. For details of the oscillation stop detection function, refer to 9. Clock Generation Circuit.
11.1.3.3
Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit.
11.1.3.4
Single-Step Interrupt, Address Break Interrupt
Do not use the single-step interrupt. For development tools only.
11.1.3.5
Address Match Interrupt
The address match interrupt is generated immediately before executing an instruction that is stored into an address indicated by the RMAD0 to RMAD1 registers when the AIER0 or AIER1 bit in the AIER register which is set to "1" (address match interrupt enable). For details of the address match interrupt, refer to 11.4 Address Match Interrupt.
11.1.4
Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function of the microcomputer and a maskable interrupt. Refer to Table 11.2 Relocatable Vector Tables for the interrupt factor of the peripheral function interrupt. For details of the peripheral function, refer to the description of each peripheral function.
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11. Interrupt
11.1.5
Interrupts and Interrupt Vector
There are 4 bytes in one vector. Set the starting address of interrupt routine in each vector table. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 11.2 shows the Interrupt Vector.
MSB
LSB
Vector Address (L)
Low Address Mid Address 0000 High Address 0000
Vector Address (H)
0000
Figure 11.2
Interrupt Vector
11.1.5.1
Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 11.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to 18.3 Functions To Prevent Flash Memory from Rewriting. Table 11.1 Fixed Vector Tables Remarks Interrupt on UND instruction Interrupt on INTO instruction If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. Reference R8C/Tiny series software manual
Vector Addresses Address (L) to (H) Undefined Instruction 0FFDCh to 0FFDFh Interrupt Source Overflow BRK Instruction 0FFE0h to 0FFE3h 0FFE4h to 0FFE7h
Address Match Single Step(1) * Watchdog Timer * Oscillation Stop Detection * Voltage Monitor 2 Address Break(1) (Reserved) Reset
0FFE8h to 0FFEBh 0FFECh to 0FFEFh 0FFF0h to 0FFF3h
11.4 Address Match Interrupt * 12. Watchdog Timer * 9. Clock Generation Circuit * 6. Voltage Detection Circuit
0FFF4h to 0FFF7h 0FFF8h to 0FFFBh 0FFFCh to 0FFFFh 5. Reset
1. Do not use the single-step interrupt. For development tools only.
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11. Interrupt
11.1.5.2
Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 11.2 lists the Relocatable Vector Tables. Table 11.2 Relocatable Vector Tables Vector Address(1) Address (L) to Address (H) +0 to +3(0000h to 0003h) +52 to +55(0034h to 0037h) +56 to +59(0038h to 003Bh) +60 to +63(003Ch to 003Fh) Software Reference Interrupt Number 0 R8C/Tiny Series software manual 1 to 12 13 14 15 11.3 Key Input Interrupt 16. A/D Converter 15. Clock Synchronous Serial I/O with Chip Select (SSU) 13.3 Timer C 14. Serial Interface
Interrupt Factor BRK Instruction(2) -(Reserved) Key Input A/D Converter SSU
Compare 1 UART0 Transmit UART0 Receive -(Reserved) -(Reserved) -(Reserved) Timer X -(Reserved) Timer Z INT1 INT3 Timer C Compare 0 INT0 -(Reserved) -(Reserved)
+64 to +67(0040h to 0043h) +68 to +71(0044h to 0047h) +72 to +75(0048h to 004Bh)
+88 to +91(0058h to 005Bh) +96 to +99(0060h to 0063h) +100 to +103(0064h to 0067h) +104 to +107(0068h to 006Bh) +108 to +111(006Ch to 006Fh) +112 to +115(0070h to 0073h) +116 to +119(0074h to 0077h)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 63
13.1 Timer X 13.2 Timer Z 11.2 INT interrupt 13.3 Timer C 11.2 INT interrupt
Software Interrupt(2) +128 to +131(0080h to 0083h) to +252 to +255(00FCh to 00FFh)
R8C/Tiny Series software manual
NOTES: 1. These addresses are relative to those in the INTB register. 2. The I flag does not disable these interrupts.
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11. Interrupt
11.1.6
Interrupt Control
The following describes enable/disable the maskable interrupts and set the priority order to acknowledge. The contents explained does not apply to the nonmaskable interrupts. Use the I flag in the FLG register, IPL and the ILVL2 to ILVL0 bits in each interrupt control register to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 11.3 shows the Interrupt Control Register and Figure 11.4 shows the INT0IC Register
Interrupt Control Register(2)
Symbol KUPIC ADIC SSUAIC CMP1IC S0TIC S0RIC TXIC TZIC INT1IC INT3IC TCIC CMP0IC Bit Symbol ILVL0 Address 004Dh 004Eh 004Fh 0050h 0051h 0052h 0056h 0058h 0059h 005Ah 005Bh 005Ch Bit Name Interrupt Priority Level Select Bit After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Function
b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
RW RW
ILVL1
ILVL2 Interrupt Request Bit
0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt
RW
RW
IR -- (b7-b4)
RW(1) --
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
NOTES : 1. Only "0" can be w ritten to the IR bit. Do not w rite " 1". 2. To rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not generated. Refer to 20.2.6 Changing Interrupt Control Registers.
Figure 11.3
Interrupt Control Register
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11. Interrupt
INT0 Interrupt Control Register(2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INT01C Bit Symbol ILVL0
Address 005Dh Bit Name Interrupt Priority Level Select Bit
After Reset XX00X000b Function
b2 b1 b0
RW RW
ILVL1
ILVL2 Interrupt Request Bit Polarity Sw itch Bit(4) Reserved Bit
0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt 0 : Selects falling edge 1 : Selects rising edge(3) Set to "0"
RW
RW
IR POL -- (b5) -- (b7-b6)
RW(1) RW RW --
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
NOTES : 1. Only "0" can be w ritten to the IR bit. (Do not w rite "1".) 2. To rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not generated. Refer to 20.2.6 Changing Interrupt Control Registers. 3. If the INTOPL bit in the INTEN register is set to "1" (both edges), set the POL bit to "0" (selects falling edge). 4. The IR bit may be set to "1" (requests interrupt) w hen the POL bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor.
Figure 11.4
INT0IC Register
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11. Interrupt
11.1.6.1
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (enabled) enables the maskable interrupt. Setting the I flag to "0" (disabled) disables all maskable interrupts.
11.1.6.2
IR Bit
The IR bit is set to "1" (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to "0" (= interrupt not requested). The IR bit can be set to "0" by a program. Do not write "1" to this bit.
11.1.6.3
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 11.3 lists the Settings of Interrupt Priority Levels and Table 11.4 lists the Interrupt Priority Levels Enabled by IPL. The following are conditions under which an interrupt is acknowledged: * I flag = 1 * IR bit = 1 * interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. They do not affect one another.
Table 11.3
ILVL2 to ILVL0 Bits 000b 001b 010b 011b 100b 101b 110b 111b
Settings of Interrupt Priority Levels
Interrupt Priority Level Priority Order - Level 0 (interrupt disabled) Level 1 Low Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High
Table 11.4
IPL 000b 001b 010b 011b 100b 101b 110b 111b
Interrupt Priority Levels Enabled by IPL
Enabled Interrupt Priority Levels Interrupt level 1 and above Interrupt level 2 and above Interrupt level 3 and above Interrupt level 4 and above Interrupt level 5 and above Interrupt level 6 and above Interrupt level 7 and above All maskable interrupts are disabled
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11. Interrupt
11.1.6.4
Interrupt Sequence
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, in regards to the SMOVB, SMOVF, SSTR or RMPA instruction, if an interrupt request is generated while executing the instruction, the microcomputer suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as follows. Figure 11.5 shows the Time Required for Executing Interrupt Sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading the address 00000h. The IR bit for the corresponding interrupt is set to "0" (interrupt not requested). (2) The FLG register immediately before entering the interrupt sequence is saved to the CPU internal temporary register(1). (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to "0" (disables interrupts). The D flag is set to "0" (disables single-step interrupt). The U flag is set to "0" (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt numbers 32 to 63 is executed. (4) The CPU's internal temporary register(1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, the instructions are executed from the starting address of the interrupt routine. NOTES: 1. This register cannot be used by user.
1 CPU Clock Address Bus Data Bus RD WR
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Address 0000h Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2 SP-1
SP-4
SP-3
SP-3 contents
VEC
VEC contents
VEC+1
VEC+1 contents
VEC+2
VEC+2 contents
PC
SP-2 SP-1 SP-4 contents contents contents
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions.
Figure 11.5
Time Required for Executing Interrupt Sequence
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11. Interrupt
11.1.6.5
Interrupt Response Time
Figure 11.6 shows an Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in an interrupt routine. An interrupt response time includes the period between an interrupt request generation and the completed execution of an instruction (see #a in Figure 11.6) and the period required to perform an interrupt sequence (20 cycles, see #b in Figure 11.6).
Interrupt request is generated Interrupt request is acknowledged
Time
Instruction
(a)
Interrupt Sequence
20 Cycles (b)
Instruction in interrupt routine
Interrupt Response Time
(a) Period between an interrupt request generation and the completed execution of an instruction. The length of this time varies depending on the instruction being executed. The DIVX instruction requires the longest time; 30 cycles (no wait and when the register is set as the divisor) (b) 21 cycles for address match and single-step interrupts.
Figure 11.6
Interrupt Response Time
11.1.6.6
IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt and special interrupt request are acknowledged, the level listed in Table 11.5 is set to the IPL. Table 11.5 lists the IPL Value When Software or Special Interrupts Is Acknowledged. Table 11.5 IPL Value When Software or Special Interrupts Is Acknowledged
Interrupt Factor Value Set to IPL Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 2 7 Software, Address Match, Single-Step Not changed
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11. Interrupt
11.1.6.7
Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack. After 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, extended to 16 bits, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 11.7 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used(1) with 1 instruction. NOTES: 1. Selectable from the R0, R1, R2, R3, A0, A1, SB and FB registers.
Address
MSB
Stack
LSB
Address
MSB
Stack
LSB
m-4 m-3
m-4 m-3
PCL PCM FLGL FLGH PCH
[SP] New SP Value
m-2 m-1 m
m-2 m-1
Content of Previous Stack Content of Previous Stack
[SP] SP value before interrupt is generated
m
Content of Previous Stack Content of Previous Stack
m+1
m+1
PCH PCM PCL FLGH FLGL
: High-order 4 bits of PC : Middle-order 8 bits of PC : Low-order 8 bits of PC : High-order 4 bits of FLG : Low-order 8 bits of FLG
Stack state before interrupt request is acknowledged
Stack state after interrupt request is acknowledged
NOTES 1.When executing the software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP.
Figure 11.7
Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation which is performed in the interrupt sequence is saved in 8 bits every 4 steps. Figure 11.8 shows the Operation of Saving Register.
Address Stack
Sequence in which order registers are saved
[SP]-5 [SP]-4 [SP]-3
PCL PCM FLGL FLGH PCH
(3) (4)
Saved, 8 bits at a time
[SP]-2 [SP]-1 (1) (2)
[SP]
completed saving registers in four operations.
PCH PCM PCL FLGH FLGL
: High-order 4 bits of PC : Middle-order 8 bits of PC : Low-order 8 bits of PC : High-order 4 bits of FLG : Low-order 8 bits of FLG
NOTES : 1. [SP] indicates the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. When executing the
software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP.
Figure 11.8
Operation of Saving Register Page 66 of 253
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11. Interrupt
11.1.6.8
Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically returned. The program, executed before the interrupt request has been acknowledged, starts running again. Return the register saved by a program in an interrupt routine using the POPM instruction or others before the REIT instruction.
11.1.6.9
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt with the higher priority is acknowledged. Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral functions). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the higher priority interrupt acknowledged in hardware. The priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are set by hardware. Figure 11.9 shows the Interrupt Priority Levels of Hardware Interrupt. The interrupt priority does not affect software interrupts. The microcomputer jumps to the interrupt routine when the instruction is executed.
Reset Watchdog Timer Oscillation Stop Detection Voltage Monitor 2 Peripheral Function Single Step Address Match
High
Low
Figure 11.9
Interrupt Priority Levels of Hardware Interrupt
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11. Interrupt
11.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority judgement circuit selects the highest priority interrupt. Figure 11.10 shows the Judgement Circuit of Interrupts Priority Level.
Priority Level of Each Interrupt
Level 0 (default value)
Highest
Compare 0 INT3 Timer Z Timer X INT0 Timer C INT1 UART0 Receive Compare 1 A/D Conversion UART0 Transmit SSU Key Input IPL Lowest Interrupt request level judgment output signal I flag Address Match Watchdog Timer Oscillation Stop Detection Voltage Monitor 2 Interrupt request acknowledged
Priority of peripheral function interrupts (if priority levels are same)
Figure 11.10
Judgement Circuit of Interrupts Priority Level
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11. Interrupt
11.2 11.2.1
INT Interrupt INT0 Interrupt
The INT0 interrupt is generated by an INT0 input. When using the INT0 interrupt, the INT0EN bit in the INTEN register is set to "1" (enable). The edge polarity is selected using the INT0PL bit in the INTEN register and the POL bit in the INT0IC register. Inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the external trigger input pin of timer Z. Figure 11.11 shows the INTEN and INT0F Registers.
External Input Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol INTEN Bit Symbol INT0EN INT0PL -- (b7-b2)
Address 0096h Bit Name _____ INT0 Input Enable Bit(1)
_____
After Reset 00h Function 0 : Disable 1 : Enable 0 : One edge 1 : Both edges Set to "0"
RW RW RW RW
INT0 Input Polarity Select Bit(2,3) Reserved Bit
NOTES : 1. Set the INT0EN bit w hile the INOSTG bit in the PUM register is set to "0" (one-shot trigger disabled). 2. When setting the INT0PL bit to "1" (both edges), set the POL bit in the INT0IC register to "0" (selects falling edge). 3. The IR bit in the INT0IC register may be set to "1" (requests interrupt) w hen the INT0PL bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor.
_______
INT0 Input Filter Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INT0F Bit Symbol
_____
Address 001Eh Bit Name INT0 Input Filter Select Bit
b1 b0
After Reset 00h Function 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling Set to "0"
RW RW
INT0F0
INT0F1 -- (b2) -- (b7-b3) Reserved Bit
RW
RW --
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
Figure 11.11
INTEN and INT0F Registers
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11. Interrupt
11.2.2
INT0 Input Filter
The INT0 input contains a digital filter. The sampling clock is selected by the INT0F1 to INT0F0 bits in the INT0F register. The IR bit in the INT0IC register is set to "1" (interrupt requested) when the INT0 level is sampled for every sampling clock and the sampled input level matches three times. Figure 11.12 shows the Configuration of INT0 Input Filter. Figure 11.13 shows the Operating Example of INT0 Input Filter.
INT0F1 to INT0F0
f1 f8 f32
=01b =10b =11b Sampling Clock INT0EN
Other than INT0F1 to INT0F0 =00b
INT0 Port P4_5 Direction Register
Digital Filter (input level matches 3x)
INT0 Interrupt
INT0PL=0
=00b
INT0F0, INT0F1 : Bits in INT0F register INT0EN, INT0PL : Bits in INTEN register
Both Edges Detection INT0PL=1 Circuit
Figure 11.12
Configuration of INT0 Input Filter
INT0 input Sampling timing
IR bit in INT0IC register
Set to "0" in program This is an operation example when the INT0F1 to INT0F0 bits in the INT0F register is set to "01b", "10b", or "11b" (passing digital filter).
Figure 11.13
Operating Example of INT0 Input Filter
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11. Interrupt
11.2.3
INT1 Interrupt
The INT1 interrupt is generated by INT1 inputs. The edge polarity is selected by the R0EDG bit in the TXMR register. When the CNTRSEL bit in the UCON register is set to "0", the INT10 pin becomes the INT1 input pin. When the CNTRSEL bit is set to "1", the INT11 pin becomes the INT1 input pin. The INT10 pin is shared with the CNTR00 pin and the INT11 pin is shared with the CNTR01 pin. Figure 11.14 shows the TXMR Register when INT1 Interrupt is Used.
Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TXMR Bit Symbol TXMOD0
TXMOD1
Address After Reset 008Bh 00h Bit Name Function Operating Mode Select Bit 0, b1 b0 0 0 : Timer mode or pulse period measurement 1(1) mode 0 1 : Do not set 1 0 : Event count mode 1 1 : Pulse w idth measurement mode INT1/CNTR0 Polarity Sw itch 0 : Rising edge 1 : Falling edge Bit(2) 0 : Stops counting Timer X Count Start Flag(3) 1 : Starts counting
________ _____
RW RW
RW
R0EDG TXS TXOCNT
RW RW RW
P3_7/CNTR0 Select Bit Operating Mode Select Bit 2
Function varies depending on operating mode 0 : Other than pulse period measurement mode 1 : Pulse period measurement mode
TXMOD2
RW
TXEDG TXUND
Active Edge Reception Flag Function varies depending on operating mode Timer X Underflow Flag Function varies depending on operating mode
RW RW
NOTES : _____ 1. When using INT1 interrupt, select modes other than pulse output mode. 2. The IR bit in the INT1IC register may be set to "1" (requests interrupt) w hen the R0EDG bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor. 3. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
Figure 11.14
TXMR Register when INT1 Interrupt is Used
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11. Interrupt
11.2.4
INT3 Interrupt
The INT3 interrupt is generated by the INT3 input. Set the TCC07 bit in the TCC0 register to "0" (INT3). When the TCC06 bit in the TCC0 register is set to "0", the INT3 interrupt request is generated synchronizing with the count source of timer C. When the TCC06 bit is set to "1", the INT3 interrupt request is generated when the INT3 is input. The INT3 input contains a digital filter. The IR bit in the INT3IC register is set to "1" (interrupt requested) when the INT3 level is sampled for every sampling clock and the sampled input level matches three times. The sampling clock is selected by the TCC11 to TCC10 bits in the TCC1 register. When selecting "Filter", the interrupt request is generated synchronizing with the sampling clock even if the TCC06 bit is set to "1". The P3_3 bit in the P3 register indicates the previous value before filtering regardless of the contents set in the TCC11 to TCC10 bits. The INT3 pin is used with the TCIN pin. When setting the TCC07 bit to "1" (fRING128), the INT3 interrupt is generated by the fRING128 clock. The IR bit in the INT3IC register is set to "1" (interrupt requested) every fRING128 clock cycle or every half fRING128 clock cycle. Figure 11.15 shows the TCC0 Register and Figure 11.16 shows the TCC1 Register.
Timer C Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TCC0 Bit Symbol TCC00
Address 009Ah Bit Name Timer C Count Start Bit Timer C Count Source Select Bit(1)
After Reset 00h Function 0 : Stops counting 1 : Starts counting
b2 b1
RW RW
TCC01
TCC02
_____
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fRING-fast
RW
RW
TCC03
INT3 Interrupt and Capture Polarity Select Bit
(1,2)
b4 b3
TCC04 -- (b5) Reserved Bit
_____
0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Do not set Set to "0"
_____
RW
RW
RW
TCC06
INT3 Interrupt Request Generation Timing Select Bit(2,3)
0 : INT3 Interrupt is generated synchronizing w ith Timer C count
_____
_____
TCC07
INT3 Interrupt and Capture Input Sw itch Bit(1,2)
1 : INT3 Interrupt is generated w hen _____ INT3 interrupt is input(4) _____ 0 : INT3 1 : fRING128
RW
RW
NOTES : 1. Change this bit w hen the TCC00 bit is set to "0" (count stop). 2. The IR bit in the INT3IC register may be set to "1" (requests interrupt) w hen the TCC03, TCC04, TCC06 and TCC07 bits are rew ritten. Refer to 20.2.5 Changing Interrupt Factor.
_____
3. When the TCC13 bit is set to "1" (output compare mode) and INT3 interrupt is input, regardless of the setting value of the TCC06 bit, an interrupt request is generated. _____ _____ 4. When using INT3 filter, the INT3 interrupt is generated synchronizing w ith the clock for the digital filter.
Figure 11.15
TCC0 Register
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11. Interrupt
Timer C Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCC1 Bit Symbol TCC10
_____
Address 009Bh Bit Name
b1b0
After Reset 00h Function 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW RW
INT3 Filter Select Bit(1)
TCC11
RW
TCC12
Timer C Counter Reload Select 0 : No reload Bit(2,3) 1 : Set TC register to "0000h" w hen compare 1 is matched Compare 0 / Capture Select Bit 0 : Capture Select (input capture mode) 1 : Compare 0 Output Select (output compare mode)
(2)
RW
TCC13
RW
TCC14
TCC15
Compare 0 Output Mode Select b5 b4 Bit(3) 0 0 : CMP output remains unchanged even w hen compare 0 is matched 0 1 : CMP output is reversed w hen compare 0 signal is matched 1 0 : CMP output is set to "L" w hen compare 0 signal is matched 1 1 : CMP output is set to "H" w hen compare 0 signal is matched Compare 1 Output Mode Select b7 b6 Bit(3) 0 0 : CMP output remains unchanged even w hen compare 1 is matched 0 1 : CMP output is reversed w hen compare 1 signal is matched 1 0 : CMP output is set to "L" w hen compare 1 signal is matched 1 1 : CMP output is set to "H" w hen compare 1 signal is matched
RW
RW
TCC16
RW
TCC17
RW
NOTES : _____ 1. When the same value from the INT3 pin is sampled three times continuously, the input is determined. 2. When the TCC00 bit in the TCC0 register is set to "0" (count stop), rew rite the TCC13 bit. 3. When the TCC13 bit is set to "0" (input capture mode), set the TCC12, TCC14 to TCC17 bits to "0".
Figure 11.16
TCC1 Register
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11. Interrupt
11.3
Key Input Interrupt
A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i=0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in the KIEN register can select the input polarity. When inputting "L" to the KIi pin which sets the KIiPL bit to "0" (falling edge), the input of the other K10 to K13 pins are not detected as interrupts. Also, when inputting "H" to the KIi pin which sets the KIiPL bit to "1" (rising edge), the input of the other K10 to K13 pins are not detected as interrupts. Figure 11.17 shows a Block Diagram of Key Input Interrupt.
PU02 bit in PUR0 register Pull-Up Transistor KUPIC Register PD1_3 bit in PD1 register KI3EN Bit PD1_3 Bit KI3PL=0 KI3 KI3PL=1 Pull-Up Transistor KI2 KI2PL=1 Pull-Up Transistor KI1 KI1PL=1 Pull-Up Transistor KI0 KI0PL=1 KI0EN Bit PD1_0 Bit KI0PL=0 KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register KI1EN Bit PD1_1 Bit KI1PL=0 KI2EN Bit PD1_2 Bit KI2PL=0 Interrupt Control Circuit Key Input Interrupt Request
Figure 11.17
Block Diagram of Key Input Interrupt
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11. Interrupt
Key Input Enable Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL
Address 0098h Bit Name KI0 Input Enable Bit KI0 Input Polarity Select Bit KI1 Input Enable Bit KI1 Input Polarity Select Bit KI2 Input Enable Bit KI2 Input Polarity Select Bit KI3 Input Enable Bit KI3 Input Polarity Select Bit
After Reset 00h Function 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge
RW RW RW RW RW RW RW RW RW
NOTES : 1. The IR bit in the KUPIC register may be set to "1" (requests interrupt) w hen the KIEN register is rew ritten. Refer to 20.2.5 Changing Interrupt Factor.
Figure 11.18
KIEN Register
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11. Interrupt
11.4
Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). This interrupt is used for a break function of the debugger. When using the on-chip debugger, do not set an address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system. Set the starting address of any instruction in the RMADi register. The AIER0 and AIER1 bits in the AIER0 register can select to enable or disable the interrupt. The I flag and IPL do not affect the address match interrupt. The value of the PC (Refer to 11.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the RMADi register (The appropriate return address is not pushed on the stack). When returning from the address match interrupt, return by one of the following: * Change the content of the stack and use the REIT instruction. * Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowledged. And then use a jump instruction. Table 11.6 lists the Value of PC Saved to Stack when Address Match Interrupt is Acknowledged. Figure 11.19 shows the AIER, RMAD0 to RMAD1 Registers. Table 11.6 Value of PC Saved to Stack when Address Match Interrupt is Acknowledged PC Value Saved(1) Address indicated by RMADi register + 2
Address Indicated by RMADi Register (i=0,1) * 16-bit operation code instruction * Instruction shown below among 8-bit operation code instructions ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest = A0 or A1) * Instructions other than the above NOTES: 1. Refer to the 11.1.6.7 Saving a Register for the PC value saved. Table 11.7
Address indicated by RMADi register + 1
Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Factor Address Match Interrupt Enable Bit Address Match Interrupt Register Address Match Interrupt 0 AIER0 RMAD0 Address Match Interrupt 1 AIER1 RMAD1
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11. Interrupt
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit Symbol AIER0 AIER1 -- (b7-b2)
Address 0009h Bit Name Address Match Interrupt 0 Enable Bit 0 : Disable 1 : Enable Address Match Interrupt 1 Enable Bit 0 : Disable 1 : Enable Nothing is assigned. When w rite, set to "0". When read, its content is "0".
After Reset 00h Function
RW RW RW --
Address Match Interrupt Register i(i=0,1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1 Function
Address 0012h-0010h 0016h-0014h
After Reset X00000h X00000h Setting Range 00000h to FFFFFh RW RW --
Address setting register for address match interrupt -- Nothing is assigned. When w rite, set to "0". (b7-b4) When read, its content is indeterminate.
Figure 11.19
AIER, RMAD0 to RMAD1 Registers
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12. Watchdog Timer
12. Watchdog Timer
The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can select count source protection mode is enabled or disabled. Table 12.1 lists the Count Source Protection Mode is Enabled / Disabled Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset. Figure 12.1 shows the Block Diagram of Watchdog Timer and Figures 12.2 to 12.3 show the OFS, WDC, WDTR, WDTS and CSPR Registers. Table 12.1 Count Source Protection Mode is Enabled / Disabled Item Count Source Count Operation Reset Condition of Watchdog Timer Count Start Condition When Count Source Protection Mode is Disabled CPU clock When Count Source Protection Mode is Enabled Low-speed on-chip oscillator clock
Count Stop Condition Operation at the time of Underflow
Decrement * Reset * Write "00h" to the WDTR register before writing "FFh" * Underflow Either of following can be selected * After reset, count starts automatically * Count starts by writing to WDTS register Stop mode, wait mode None Watchdog timer interrupt or Watchdog timer reset watchdog timer reset
Prescaler
1/16 CPU Clock 1/128
WDC7=0 CSPRO=0 PM12=0 Watchdog Timer Interrupt Request
WDC7=1
Watchdog Timer
PM12=1 Watchdog Timer Reset
fRING-S
CSPRO=1 Set to "7FFFh"(1)
Write to WDTR register Internal Reset Signal
CSPRO : Bit in CSPR register WDC7 : Bit in WDC register
NOTES: 1. When the CSPRO bit is set to "1" (count source protection mode enabled), "0FFFh" is set.
Figure 12.1
Block Diagram of Watchdog Timer
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12. Watchdog Timer
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
111
1
Symbol OFS Bit Symbol
WDTON
Address 0FFFFh Bit Name Watchdog Timer Start Select Bit
Before Shipment FFh(2) Function 0 : Watchdog timer starts automatically after reset 1 : Watchdog timer is inactive after reset
RW
RW
-- (b1) ROMCR ROMCP1 -- (b6-b4)
Reserved Bit ROM Code Protect Disabled Bit ROM Code Protect Bit Reserved Bit
Set to "1" 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to "1"
RW RW RW RW
Count Source Protection 0 : Count source protect mode enabled after reset CSPROINI Mode After Reset Select 1 : Count source protect mode disabled after reset Bit NOTES : 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. 2. If the block including the OFS register is erased, "FFh" is set to the OFS register.
RW
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol Address 000Fh WDC Bit Symbol Bit Name -- High-order Bit of Watchdog Timer (b4-b0) -- (b5) -- (b6) WDC7 Reserved Bit Reserved Bit Prescaler Select Bit Set to "0" Set to "0" 0 : Divide-by-16 1 : Divide-by-128
After Reset 00011111b Function
RW RO RW RW RW
Figure 12.2
OFS and WDC Registers
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12. Watchdog Timer
Watchdog Timer Reset Register
b7 b0
Symbol WDTR
Address 000Dh
After Reset Indeterminate RW
Function When w riting "00h" before w riting "FFh", the w atchdog timer is reset.(1) The default value of the w atchdog timer is set to "7FFFh" w hen count source protection mode is disabled and "0FFFh" w hen count source protection mode is enabled.(2) NOTES : 1. Do not generate an interrupt betw een "00h" and the "FFh" w ritings. 2. When the CSPRO bit in the CSPR register is set to "1" (count source protection mode enabled), "0FFFh" is set to the w atchdog timer.
WO
Watchdog Timer Start Register
b7 b0
Symbol WDTS
Address 000Eh
After Reset Indeterminate RW WO
Function The w atchdog timer starts counting after a w rite instruction to this register.
Count Source Protection Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Symbol Address 001Ch CSPR Bit Symbol Bit Name -- Reserved Bit (b6-b0) CSPRO
After Reset(1) 00h Function Set to "0"
RW RW RW
Count Source Protection Mode 0 : Count source protection mode disabled 1 : Count source protection mode enabled Select Bit(2)
NOTES : 1. When w riting "0" to the CSPROINI bit in the OFS register, the value after reset is set to "10000000b". 2. Write "0" before w riting "1" to set the CSPRO bit to "1". "0" cannot be set by a program.
Figure 12.3
WDTR, WDTS and CSPR Registers
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12. Watchdog Timer
12.1
When Count Source Protection Mode Disabled
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 12.2 lists the Specification of Watchdog Timer (When Count Source Protection Mode is Disabled). Table 12.2 Specification of Watchdog Timer (When Count Source Protection Mode is Disabled) Item Count Source Count Operation Period CPU clock Decrement Division ratio of prescaler(n) x count value of watchdog timer(32768)(1) CPU clock n : 16 or 128 (selected by WDC7 bit in WDC register) e.g.When the CPU clock is 16MHz and prescaler is divided by 16, the period is approximately 32.8ms The WDTON bit(2) in the OFS register (0FFFFh) selects the operation of watchdog timer after reset * When the WDTON bit is set to "1" (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after reset and the count starts by writing to the WDTS register * When the WDTON bit is set to "0" (watchdog timer starts automatically after exiting ) The watchdog timer and prescaler start counting automatically after reset * Reset * Write "00h" to the WDTR register before writing "FFh" * Underflow Stop and wait modes (inherit the count from the held value after exiting modes) * When the PM12 bit in the PM1 register is set to "0" Watchdog timer interrupt * When the PM12 bit in the PM1 register is set to "1" Watchdog timer reset (refer to 5.5 Watchdog Timer Reset) Specification
Count Start Condition
Reset Condition of Watchdog Timer Count Stop Condition Operation at the time of Underflow
NOTES: 1. The watchdog timer is reset when writing "00h" to the WDTR register before writing "FFh". The prescaler is reset after the microcomputer is reset. Some errors occur by the prescaler for the period of the watchdog timer. 2. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write "0" to the bit 0 of the address 0FFFFh by a flash writer.
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12. Watchdog Timer
12.2
When Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when the program is out of control, the clock can be supplied to the watchdog timer. Table 12.3 lists the Specification of Watchdog Timer (When Count Source Protection Mode is Enabled). Table 12.3 Specification of Watchdog Timer (When Count Source Protection Mode is Enabled) Item Count Source Count Operation Period Specification Low-speed on-chip oscillator clock Decrement Count value of watchdog timer (4096) Low-speed on-chip oscillator clock e.g. Period is approximately 32.8ms when the low-speed on-chip oscillator clock is 125 kHz The WDTON bit(1) in the OFS register (0FFFFh) selects the operation of the watchdog timer after reset. * When the WDTON bit is set to "1" (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after reset and the count starts by writing to the WDTS register * When the WDTON bit is set to "0" (watchdog timer starts automatically after reset) The watchdog timer and prescaler start counting automatically after reset * Reset * Write "00h" to the WDTR register before writing "FFh" * Underflow None (the count does not stop in wait mode after the count starts. The microcomputer does not enter stop mode) Watchdog timer reset (refer to 5.5 Watchdog Timer Reset) * When setting the CSPPRO bit in the CSPR register to "1" (count source protection mode is enabled)(2), the following are set automatically - Set 0FFFh to the watchdog timer - Set the CM14 bit in the CM1 register to "0" (low-speed on-chip oscillator on) - Set the PM12 bit in the PM1 register to "1" (The watchdog timer is reset when watchdog timer underflows) * The following states are held in count source protection mode - Writing to the CM10 bit in the CM1 register disables (It remains unchanged even if it is set to "1". The microcomputer does not enter stop mode) - Writing to the CM14 bit in the CM1 register disables (It remains unchanged even if it is set to "1". The low-speed on-chip oscillator does not stop)
Count Start Condition
Reset Condition of Watchdog Timer Count Stop Condition Operation at the time of Underflow Register, Bit
NOTES: 1. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write "0" to the bit 0 of the address 0FFFFh by a flash writer. 2. Even if writing "0" to the CSPROINI bit in the OFS register, the CSPRO bit is set to "1". The CSPROINI bit cannot be changed by a program. When setting the CSPROINI bit, write "0" to the bit 7 of the address 0FFFFh by a flash writer. Rev.2.10 Jan 19, 2006 REJ09B0164-0210 Page 82 of 253
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13. Timers
13. Timers
The microcomputer contains two 8-bit timers with 8-bit prescaler and a 16-bit timer. The two 8-bit timers with the 8-bit prescaler contain Timer X and Timer Z. These timers contain a reload register to memorize the default value of the counter. The 16-bit timer is Timer C which contains the input capture and output compare. All these timers operate independently. The count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading. Table 13.1 lists Functional Comparison of Timers. Table 13.1 Configuration Functional Comparison of Timers Item Timer X 8-bit timer with 8-bit prescaler (with reload register) Decrement * f1 * f2 * f8 * fRING provided provided provided provided provided not provided not provided not provided not provided not provided CNTR0 CNTR0 CNTR0 Timer X interrupt INT1 interrupt Timer Z 8-bit timer with 8-bit prescaler (with reload register) Decrement * f1 * f2 * f8 * Timer X underflow provided not provided not provided not provided not provided provided provided provided not provided not provided INT0 TZOUT Timer Y interrupt INT0 interrupt Timer C 16-bit free-run timer (with input capture and output compare) Increment * f1 * f8 * f32 * fRING-fast not provided not provided not provided not provided not provided not provided not provided not provided provided provided TCIN CMP0_0 to CMP0_2 CMP1_0 to CMP1_2 Timer C interrupt INT3 interrupt Compare 0 interrupt Compare 1 interrupt provided
Count Count source
Function
Timer Mode Pulse Output Mode Event Counter Mode Pulse Width Measurement Mode Pulse Period Measurement Mode Programmable Waveform Generation Mode Programmable one-shot generation mode Programmable Wait OneShot Generation Mode Input Capture Mode Output Compare Mode
Input Pin Output Pin Related Interrupt
Timer Stop
provided
provided
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13. Timers
13.1
Timer X
Timer X is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. The reload register and counter are allocated at the same address. When accessing the PREX and TX registers, the reload register and counter can be accessed (Refer to Tables 13.2 to 13.6 the Specification of Each Modes). Figure 13.1 shows the Block Diagram of Timer X. Figures 13.2 and 13.3 show the registers associated with Timer X. Timer X contains five operating modes listed as follows: * Timer mode: The timer counts an internal count source. * Pulse output mode: The timer counts an internal count source and outputs the pulses which inverts the polarity by underflow of the timer. * Event counter mode: The timer counts external pulses. * Pulse width measurement mode: The timer measures the pulse width of an external pulse * Pulse period measurement mode: The timer measures the pulse period of an external pulse.
Data bus TXCK1 to TXCK0 f1 f8 fRING f2
CNTRSEL=1
=00b =01b =10b =11b
TXMOD1 to TXMOD0 =00b or 01b
=11b
Reload register
Reload register
Counter
=10b
Counter TX register
Timer X interrupt
PREX register TXS bit
INT11/CNTR01 INT10/CNTR00
CNTRSEL=0
Polarity switching
INT1 interrupt R0EDG=1
Q Toggle flip-flop CLR CK Q
TXMOD1 to TXMOD0 bits=01b
TXOCNT bit CNTR0
R0EDG=0
Write to TX register TXMOD1 to TXMOD0 bits=01b TXMOD0 to TXMOD1, R0EDG, TXS, TXOCNT : Bits in TXMR register TXCK0 to TXCK1 : Bits in TCSS register CNTRSEL : Bit in UCON register
Figure 13.1
Block Diagram of Timer X
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Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TXMR Bit Symbol TXMOD0
Address 008Bh Bit Name Operating Mode Select Bit 0, 1
After Reset 00h Function
b1 b0
RW RW
TXMOD1
_____
0 0 : Timer mode or pulse period measurement mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse w idth measurement mode INT1/CNTR0 Signal Polarity Sw itch Bit(1) Timer X Count Start Flag(2)
________
RW
R0EDG TXS TXOCNT
Function varies depending on operating mode 0 : Stops counting 1 : Starts counting Function varies depending on operating mode 0 : Other than pulse period measurement mode 1 : Pulse period measurement mode Function varies depending on operating mode Function varies depending on operating mode
RW RW RW
P3_7/CNTR0 Select Bit Operating Mode Select Bit 2
TXMOD2 Active Edge Reception Flag Timer X Underflow Flag
RW
TXEDG TXUND
RW RW
NOTES : 1. The IR bit in the INT1IC register may be set to "1" (requests interrupt) w hen the R0EDG bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor. 2. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
Figure 13.2
TXMR Register
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Prescaler X Register
b7 b0
Symbol PREX Mode Timer Mode Pulse Output Mode Event Counter Mode Pulse Width Measurement Mode Pulse Period Measurement Mode
Address 008Ch Function Counts internal count source Counts internal count source Counts input pulses from external Measures pulse w idth of input pulses from external (counts internal count source) Measures pulse period of input pulses from external (counts internal count source)
After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh
RW RW RW RW
00h to FFh
RW
00h to FFh
RW
Timer X Register
b7 b0
Symbol TX Function Counts underflow of Prescaler X
Address 008Dh
After Reset FFh Setting Range 00h to FFh
RW RW
Timer Count Source Setting Register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol TCSS Bit Symbol TXCK0
TXCK1 -- (b3-b2) TZCK0
Address 008Eh Bit Name Timer X Count Source Select b1 b0 0 0 : f1 Bit(1) 0 1 : f8 1 0 : fRING 1 1 : f2 Reserved Bit Set to "0"
After Reset 00h Function
RW RW
RW
RW RW
TZCK1 -- (b7-b6)
Timer Z Count Source Select b5 b4 Bit(1) 0 0 : f1 0 1 : f8 1 0 : Selects Timer X underflow 1 1 : f2 Reserved Bit Set to "0"
RW
RW
NOTES : 1. Do not sw itch a count source during a count operation. Stop the timer count before sw itching a count source.
Figure 13.3
PREX, TX and TCSS Registers
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13.1.1
Timer Mode
Timer mode is mode to count the count source which is internally generated (See Table 13.2 Specification of Timer Mode). Figure 13.4 shows the TXMR Register in Timer Mode. Table 13.2 Specification of Timer Mode Specification f1, f2, f8, fRING * Decrement * When the timer underflows, the contents in the reload register is reloaded and the count is inherited 1/(n+1)(m+1) n: setting value of PREX register, m: setting value of TX register Write "1" (count starts) to the TXS bit in the TXMR register Write "0" (count stops) to the TXS bit in the TXMR register When Timer X underflows [Timer X interrupt] Programmable I/O port, or INT1 interrupt input
Item Count Source Count Operation
Divide Ratio Count Start Condition Count Stop Condition Interrupt Request Generation Timing INT10/CNTR00, INT11/CNTR01 Pin Function CNTR0 Pin Function Read from Timer Write to Timer
Programmable I/O port The count value can be read by reading the TX and PREX registers * When writing to the TX and PREX registers while the count stops, the value is written to both the reload register and counter. * When writing to the TX and PREX registers during the count, the value is written to each reload register of the TX and PREX registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input.
Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
00000
00
Symbol TXMR Bit Symbol TXMOD0 TXMOD1
Address 008Bh Bit Name Operating Mode Select Bit 0, 1
After Reset 00h Function
b1 b0
RW RW RW
0 0 : Timer mode or pulse period measurement mode
_____
R0EDG TXS TXOCNT TXMOD2 TXEDG TXUND
INT1/CNTR0 Signal Polarity Sw itch Bit(1, 2) Timer X Count Start Flag(3) Set to "0" in timer mode Operating Mode Select Bit 2 Set to "0" in timer mode Set to "0" in timer mode
0 : Rising edge 1 : Falling edge 0 : Stops counting 1 : Starts counting 0 : Other than pulse period measurement mode
RW RW RW RW RW RW
NOTES : 1. The IR bit in the INT1IC register may be set to "1" (requests interrupt) w hen the R0EDG bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor.
_____
2. This bit is used to select the polarity of INT1 interrupt in timer mode. 3. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
Figure 13.4
TXMR Register in Timer Mode
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13.1.2
Pulse Output Mode
Pulse output mode is mode to count the count source internally generated and outputs the pulse which inverts the polarity from the CNTR0 pin each time the timer underflows (See Table 13.3 Specification of Pulse Output Mode). Figure 13.5 shows TXMR Register in Pulse Output Mode. Table 13.3 Specification of Pulse Output Mode Specification f1, f2, f8, fRING * Decrement * When the timer underflows, the contents in the reload register is reloaded and the count is inherited 1/(n+1)(m+1) n: setting value of PREX register, m: setting value of TX register Write "1" (count starts) to the TXS bit in the TXMR register Write "0" (count stops) to the TXS bit in the TXMR register When Timer X underflows [Timer X interrupt] Pulse output Programmable I/O port or inverted output of CNTR0 The count value can be read by reading the TX and PREX registers. * When writing to the TX and PREX registers while the count stops, the value is written to both the reload register and counter. * When writing to the TX and PREX registers during the count, the value is written to each reload register of the TX and PREX registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input. * INT1/CNTR0 signal polarity switch function The R0EDG bit can select the polarity level when the pulse output starts(1) * Inverted pulse output function The pulse which inverts the polarity of the CNTR0 output can be output from the CNTR0 pin (selected by TXOCNT bit)
Item Count Source Count Operation
Divide Ratio Count Start Condition Count Stop Condition Interrupt Request Generation Timing INT10/CNTR00 Pin Function CNTR0 Pin Function Read from timer Write to Timer
Select Function
NOTES: 1. The level of the output pulse becomes the level when the pulse output starts when the TX register is written to.
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Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
000
01
Symbol TXMR Bit Symbol TXMOD0 TXMOD1
Address 008Bh Bit Name Operating Mode Select Bit 0, 1
After Reset 00h Function
b1 b0
RW RW RW
0 1 : Pulse output mode
_____
R0EDG TXS TXOCNT TXMOD2 TXEDG TXUND
INT1/CNTR0 Signal Polarity Sw itch Bit(1) Timer X Count Start Flag(2)
________
0 : CNTR0 signal output starts at "H" 1 : CNTR0 signal output starts at "L" 0 : Stops counting 1 : Starts counting 0 : Port P3_7
________
RW RW RW RW RW RW
P3_7/CNTR0 Select Bit Set to "0" in pulse output mode Set to "0" in pulse output mode Set to "0" in pulse output mode
1 : CNTR0 output
NOTES : 1. The IR bit in the INT1IC register may be set to "1" (requests interrupt) w hen the R0EDG bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor. 2. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
Figure 13.5
TXMR Register in Pulse Output Mode
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13.1.3
Event Counter Mode
Event counter mode is mode to count an external signal which inputs from the INT1/CNTR0 pin (See Table 13.4 Specification of Event Counter Mode). Figure 13.6 shows TXMR Register in Event Counter Mode. Table 13.4 Item Count Source Specification of Event Counter Mode
Specification External signal which is input to CNTR0 pin (Active edge is selectable by software) Count Operation * Decrement * When the timer underflows, the contents in the reload register is reloaded and the count is inherited Divide Ratio 1/(n+1)(m+1) n: setting value of PREX register, m: setting value of TX register Count Start Condition Write "1" (count starts) to the TXS bit in the TXMR register Count Stop Condition Write "0" (count stops) to the TXS bit in the TXMR register Interrupt Request * When Timer X underflows [Timer X interrupt] Generation Timing Count source input (INT1 interrupt input) INT10/CNTR00, INT11/CNTR01 Pin Function CNTR0 Pin Function Read from Timer Write to Timer Programmable I/O port The count value can be read by reading the TX and PREX registers. * When writing to the TX and PREX registers while the count stops, the value is written to both the reload register and counter. * When writing to the TX and PREX registers during the count, the value is written to each reload register of the TX and PREX registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input. * INT1/CNTR0 signal polarity switch function The R0EDG bit can select the active edge of the count source. * Count source input pin select function The CNTRSEL bit in the UCON register can select the CNTR00 or CNTR01 pin
Select Function
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Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
10
Symbol Address 008Bh TXMR Bit Symbol Bit Name TXMOD0 Operating Mode Select Bit 0, 1 TXMOD1
_____
After Reset 00h Function
b1 b0
1 0 : Event Counter Mode 0 : Rising edge 1 : Falling edge 0 : Stops counting 1 : Starts counting
RW RW RW RW RW RW RW RW RW
R0EDG TXS TXOCNT TXMOD2 TXEDG TXUND
INT1/CNTR0 Signal Polarity Sw itch Bit(1) Timer X Count Start Flag(2) Set to "0" Set to "0" Set to "0" Set to "0" in event counter in event counter in event counter in event counter mode mode mode mode
NOTES : 1. The IR bit in the INT1IC register may be set to "1" (requests interrupt) w hen the R0EDG bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor. 2. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
Figure 13.6
TXMR Register in Event Counter Mode
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13.1.4
Pulse Width Measurement Mode
Pulse width measurement mode is mode to measure the pulse width of an external signal which inputs from the INT1/CNTR0 pin (See Table 13.5 Specification of Pulse Width Measurement Mode). Figure 13.7 shows the TXMR Register in Pulse Width Measurement Mode. Figure 13.8 shows an Operating Example in Pulse Width Measurement Mode. Table 13.5 Specification of Pulse Width Measurement Mode Specification f1, f2, f8, fRING * Decrement * Continuously counts the selected signal only when the measurement pulse is "H" level, or conversely only "L" level. * When the timer underflows, the contents in the reload register is reloaded and the count is inherited Write "1" (count starts) to the TXS bit in the TXMR register Write "0" (count stops) to the TXS bit in the TXMR register * When Timer X underflows [Timer X interrupt] * Rising or falling of the CNTR0 input (end of measurement period) [INT1 interrupt] Measurement pulse input (INT1 interrupt input)
Item Count Source Count Operation
Count Start Condition Count Stop Condition Interrupt Request Generation Timing INT10/CNTR00, INT11/CNTR01 Pin Function CNTR0 Pin Function Read from Timer Write to Timer
Programmable I/O port The count value can be read by reading the TX and PREX registers. * When writing to the TX and PREX registers while the count stops, the value is written to both the reload register and counter. * When writing to the TX and PREX registers during the count, the value is written to each reload register of the TX and PREX registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input. * INT1/CNTR0 signal polarity switch function The R0EDG bit can select during "H" or "L" level as the input pulse measurement * Measurement pulse input pin select function The CNTRSEL bit in the UCON register can select the CNTR00 or CNTR01 pin
Select Function
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Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
11
Symbol Address 008Bh TXMR Bit Symbol Bit Name TXMOD0 Operating Mode Select Bit 0, 1 TXMOD1
_____
After Reset 00h Function
b1 b0
1 1 : Pulse w idth measurement mode [CNTR0] 0 : Measures "L" level w idth 1 : Measures "H" level w idth
_______
RW RW RW
R0EDG
INT1/CNTR0 Signal Polarity Sw itch Bit(1)
[INT1] 0 : Rising edge 1 : Falling edge TXS TXOCNT TXMOD2 TXEDG TXUND Timer X Count Start Flag(2) Set to "0" Set to "0" Set to "0" Set to "0" 0 : Stops counting 1 : Starts counting
RW
RW RW RW RW RW
in pulse w idth measurement mode in pulse w idth measurement mode in pulse w idth measurement mode in pulse w idth measurement mode
NOTES : 1. The IR bit in the INT1IC register may be set to "1" (requests interrupt) w hen the R0EDG bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor. 2. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
Figure 13.7
TXMR Register in Pulse Width Measurement Mode
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n = high-level: the contents of TX register, low-level: the contents of PREX register FFFFh n
Counter contents (hex)
Count Start
Underflow
Count Stop Count Stop
0000h Set to "1" by program TXS Bit in TXMR Register "1" "0"
Count Start Period
Measurement Pulse (CNTR0i Pin Input)
"1" "0" Set to "0" when interrupt request is acknowledged, or set by program
IR Bit in INT1IC Register
"1" "0" Set to "0" when interrupt request is acknowledged, or set by program
IR Bit in TXIC Register
"1" "0"
Conditions: "H" level width of measurement pulse is measured. (R0EDG=1) i=0 to 1
Figure 13.8
Operating Example in Pulse Width Measurement Mode
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13.1.5
Pulse Period Measurement Mode
Pulse period measurement mode is mode to measure the pulse period of an external signal which inputs from the INT1/CNTR0 pin (See Table 13.6 Specification of Pulse Period Measurement Mode). Figure 13.9 shows the TXMR Register in Pulse Period Measurement Mode. Figure 13.10 shows an Operating Example in Pulse Period Measurement Mode. Table 13.6 Specification of Pulse Period Measurement Mode Specification f1, f2, f8, fRING * Decrement * After an active edge of measurement pulse is input, contents for the read-out buffer are retained at the first underflow of prescaler X. Then timer X reloads contents in the reload register at the second underflow of prescaler X and continues counting. Write "1" (count start) to the TXS bit in the TXMR register Write "0" (count stop) to TXS bit in TXMR register * When timer X underflows or reloads [timer X interrupt] * Rising or falling of CNTR0 input (end of measurement period) [INT1 interrupt] Measurement pulse input(1) (INT1 interrupt input)
Item Count Source Count Operation
Count Start Condition Count Stop Condition Interrupt Request Generation Timing INT10/CNTR00, INT11/CNTR01 Pin Function CNTR0 Pin Function Read from Timer Write to Timer
Programmable I/O port Contents in the read-out buffer can be read by reading the TX register. The value retained in the read-out buffer is released by reading TX register. * When writing to the TX and PREX registers while the count stops, the value is written to both the reload register and counter. * When writing to the TX and PREX registers during the count, the value is written to each reload register of the TX and PREX registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input. * INT1/CNTR0 polarity switch function The R0EDG bit can select the measurement period of input pulse. * Measurement pulse input pin select function The CNTRSEL bit in the UCON register can select the CNTR00 or CNTR01 pin.
Select Function
NOTES: 1. Input the pulse whose period is longer than twice of the prescaler X period. Input the longer pulse for "H" width and "L" width than the prescaler X period. If the shorter pulse than the period is input to the CNTR0 pin, the input may be disabled.
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Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
10
00
Symbol TXMR Bit Symbol TXMOD0 TXMOD1
Address 008Bh Bit Name Operating Mode Select Bit 0, 1
After Reset 00h Function
b1 b0
RW RW RW
0 0 : Timer mode or pulse period measurement mode
_____
INT1/CNTR0 Signal Polarity Sw itch Bit(1) R0EDG
[CNTR0] 0 : Measures measurement pulse from one rising edge to next rising edge 1 : Measures measurement pulse from one falling edge to next falling edge
______
RW
[INT1] 0 : Rising edge 1 : Falling edge TXS TXOCNT TXMOD2 TXEDG(2) TXUND(2) Timer X Count Start Flag(3) 0 : Stops counting 1 : Starts counting RW RW RW RW RW
Set to "0" in pulse w idth measurement mode Operating Mode Select Bit 2 1 : Pulse period measurement mode Active Edge Reception Flag 0 : Active edge not received 1 : Active edge received Timer X underflow flag 0 : No underflow 1 : Underflow
NOTES : 1. The IR bit in the INT1IC register may be set to "1" (requests interrupt) w hen the R0EDG bit is rew ritten. Refer to 20.2.5 Changing Interrupt Factor. 2. This bit is set to "0" by w riting "0" in a program. (It remains unchanged even if w riting "1") 3. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
Figure 13.9
TXMR Register in Pulse Period Measurement Mode
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Underflow Signal of Prescaler X
Set to "1" by program
TXS Bit in TXMR Register
"1" "0"
Starts counting
CNTR0i Pin Input
"1" "0"
Timer X reloads Timer X reloads Timer X reloads
Contents of Timer X
0Fh 0Eh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 0Fh 0Eh 0Dh
(7)
01h 00h 0Fh 0Eh
Retained
Retained(7)
Contents of Read-Out Buffer1
0Fh
0Eh
0Ah 09h
Timer X read(3)
08h
0Dh
Timer X read(3)
01h 00h 0Fh 0Eh
(2)
(2)
TXEDG Bit in TXMR Register
"1" "0"
Set to "0" by program(4)
(6)
TXUND Bit in TXMR Register
"1" "0"
Set to "0" by program(5)
IR Bit in TXIC Register
"1" "0"
Set to "0" when interrupt request is acknowledged, or set by program
IR Bit in INT1IC Register
"1" "0"
Set to "0" when interrupt request is acknowledged, or set by program
Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured (R0EDG=0) with the default value of the TX register as 0Fh. i=0 to 1
NOTES : 1. The contents of the read-out buffer can be read when the TX register is read in pulse period measurement mode. 2. After an active edge of measurement pulse is input, the TXEDG bit in the TXMR register is set to "1" (active edge found) when the prescale X underflows for the second time. 3. The TX register should be read before the next active edge is input after the TXEDG bit is set to "1" (active edge found). The contents in the read-out buffer is retained until the TX register is read. If the TX register is not read before the next active edge is input, the measured result of the previous period is retained. 4. When set to "0" by program, use a MOV instruction to write "0" to the TXEDG in the TXMR register. At the same time, write "1" to the TXUND bit. 5. When set to "0" by program, use a MOV instruction to write "0" to the TXUND in the TXMR register. At the same time, write "1" to the TXEDG bit. 6. The TXUND and TXEDG bits are both set to "1" if the timer underflows and reloads on an active edge simultaneously. In this case, the validity of the TXUND bit should be determined by the contents of the read-out buffer. 7. If the CNTR0 active edge is input, when the prescaler X underflow signal is "H" level, its count value is the one of the read buffer. If "L" level, the following count value is the one of the read buffer.
Figure 13.10
Operating Example in Pulse Period Measurement Mode
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13.2
Timer Z
Timer Z is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. The reload register and counter are allocated at the same address. Refer to the Tables 13.7 to 13.12 for the Specification of Each Modes. Timer Z contains the timer Z primary and timer Z secondary as the reload register. Figure 13.11 shows the Block Diagram of Timer Z. Figures 13.12 to 13.15 show the TZMR, PREZ, TZSC, TZPR, TZOC, PUM, and TCSS registers. Timer Z contains the following four operating modes. * Timer mode: The timer counts an internal count source or Timer X underflow. * Programmable waveform generation mode: The timer outputs pulses of a given width successively * Programmable one-shot generation mode: The timer outputs one-shot pulse. * Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.
Data Bus TZSC Register TZCK1 to TZCK0 f1 f8
Timer X Underflow =00b =01b =10b =11b
TZPR Register
Reload Register
Reload Register
Reload Register
Counter PREZ Register
Counter
Timer Z Interrupt
f2
TZMOD1 to TZMOD0=10b, 11b TZS TZOS INT0 Interrupt INT0 Digital Filter
Input polarity selected to be one edge or both edges
Polarity Select
INT0PL TZMOD1 to TZMOD0=01b, 10b, 11b TZOCNT=0 TZOUT P1_3 bit in P1 Register TZOCNT=1 TZMOD0 to TZMOD1, TZS : Bits in TZMR register TZOS, TZOCNT : Bits in TZOC register INT0EN
INOSEG TZOPL=1
Q Q Toggle Flip-Flop CLR CK
TZOPL=0
TZOPL, INOSTG : Bits in PUM register TZCK0 to TZCK1 : Bits in TCSS register INT0EN, INT0PL : Bits in INTEN register
Write to TZMR Register TZMOD1 to TZMOD0 =01b, 10b, 11b
Figure 13.11
Block Diagram of Timer Z
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Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol Address 0080h TZMR Bit Symbol Bit Name Reserved Bit -- (b3-b0) TZMOD0
After Reset 00h Function Set to "0"
RW RW
TZMOD1
Timer Z Operating Mode b5 b4 Bit 0 0 : Timer mode 0 1 : Programmable w aveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable w ait one-shot generation mode Timer Z Write Control Bit Functions varies depending on operating mode Timer Z Count Start Flag(1) 0 : Stops counting 1 : Starts counting
RW
RW
TZWC TZS
RW RW
NOTES : 1. Refer to 20.4.3 Tim er Z for precautions on the TZS bit.
Figure 13.12
TZMR Register
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Prescaler Z Register
b7 b0
Symbol PREZ Mode Timer Mode Programmable Waveform Generation Mode Programmable One-shot Generation Mode Programmable Wait Oneshot Generation Mode
Address 0085h Function Counts internal count source or Timer X underflow Counts internal count source or Timer X underflow Counts internal count source or Timer X underflow Counts internal count source or Timer X underflow
After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh
RW RW RW RW RW
Timer Z Secondary Register
b7 b0
Symbol TZSC Mode Timer Mode Programmable Waveform Generation Mode Programmable One-shot Generation Mode Programmable Wait Oneshot Generation Mode Disabled
Address 0086h Function
After Reset FFh Setting Range -- 00h to FFh
RW -- WO(2) -- WO
Counts underflow of Prescaler Z(1) Disabled Counts underflow of Prescaler Z (one-shot w idth is counted)
-- 00h to FFh
NOTES : 1. Each value in the TZPR register and TZSC register is reloaded to the counter alternately and counted. 2. The count value can be read out by reading the TZPR register even w hen the secondary period is being counted.
Timer Z Primary Register
b7 b0
Symbol TZPR Mode Timer Mode Programmable Waveform Generation Mode Programmable One-shot Generation Mode Programmable Wait Oneshot Generation Mode
Address 0087h Function Counts underflow of Prescaler Z Counts underflow of Prescaler Z(1) Counts underflow of Prescaler Z (counts one-shot w idth) Counts underflow of Prescaler Z (counts w ait period)
After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh
RW RW RW RW RW
NOTES : 1. Each value in the TZPR register and TZSC register is reloaded to the counter alternately and counted.
Figure 13.13
PREZ, TZSC and TZPR Registers
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Timer Z Output Control Register(3)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TZOC Bit Symbol TZOS -- (b1) TZOCNT -- (b7-b3)
Address 008Ah Bit Name Timer Z One-shot Start Bit(1) Reserved Bit Timer Z Programmable Waveform Generation Output Sw itch Bit(2)
After Reset 00h Function 0 : One-shot stops 1 : One-shot starts Set to "0" 0 : Outputs programmable w aveform 1 : Outputs value in P1_3 port register
RW RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, its content is "0".
NOTES : 1. This bit is set to "0" w hen the output of one-shot w aveform is completed. Set the TZOS bit to "0" w hen the w aveform output is stopped by setting the TZS bit in the TZMR register to "0" (count stop) during the one-shot w aveform output. 2. This bit is enabled only w hen operating in programmable w aveform generation mode. 3. If executing an instruction w hich changes this register w hen the TZOS bit is set to "1" (during count), the TZOS bit is automatically set to "0" (one-shot stop) w hen the count is completed w hile the instruction is executed. If this causes some problems, execute an instruction w hich changes this register w hen the TZOS bit is set to "0" (one-shot stop).
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol Address 0084h PUM Bit Symbol Bit Name -- Reserved Bit (b4-b0) TZOPL INOSTG INOSEG Timer Z Output Level Latch
_____
After Reset 00h Function Set to "0" Function varies depending on operating mode
_____
RW RW RW RW RW
INT0 Pin One-shot Trigger Control Bit (Timer Z)(2) _____ INT0 Pin One-shot Trigger Polarity Select Bit (Timer Z) (1)
0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled 0 : Falling edge trigger 1 : Rising edge trigger
NOTES : 1. When the INOSEG bit is enabled only w hen the INT0PL bit in the INTEN register is set to "0" (one edge). 2. Set the INOSTG bit to "1" w hen setting the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register.
Figure 13.14
TZOC and PUM Registers
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Timer Count Source Setting Register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol TCSS Bit Symbol TXCK0
Address 008Eh Bit Name Timer X Count Source Select Bit(1)
After Reset 00h Function
b1 b0
RW RW
TXCK1 -- (b3-b2) TZCK0 Reserved Bit Timer Z Count Source Select Bit(1)
0 0 : f1 0 1 : f8 1 0 : fRING 1 1 : f2 Set to "0"
b5 b4
RW
RW RW
TZCK1 -- (b7-b6) Reserved Bit
0 0 : f1 0 1 : f8 1 0 : Selects Timer X underflow 1 1 : f2 Set to "0"
RW
RW
NOTES : 1. Do not sw itch a count source during a count operation. Stop the timer count before sw itching a count source.
Figure 13.15
TCSS Register
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13.2.1
Timer Mode
Timer mode is mode to count a count source which is internally generated or Timer X underflow (see Table 13.7 Specification of Timer Mode). The TZSC register is unused in timer mode. Figure 13.16 shows the TZMR and PUM Registers in Timer Mode. Table 13.7 Specification of Timer Mode Specification
f1, f2, f8, Timer X underflow * Decrement * When the timer underflows, it reloads the reload register contents before the count continues (When Timer Z underflows, the contents of Timer Z primary reload register is reloaded) Divide Ratio 1/(n+1)(m+1) fi: Count source frequency n: setting value in PREZ register, m: setting value in TZPR register Count Start Condition Write "1" (count starts) to the TZS bit in the TZMR register Count Stop Condition Write "0" (count stops) to the TZS bit in the TZMR register Interrupt Request * When Timer Z underflows [Timer Z interrupt] Generation Timing TZOUT Pin Function Programmable I/O port INT0 Pin Function Read from Timer Write to Timer(1) Programmable I/O port, or INT0 interrupt input The count value can be read out by reading the TZPR and PREZ registers * When writing to the TZPR and PREZ registers while the count stops, the value is written to both the reload register and counter. * When writing to the TZPR and PREZ registers during the count while the TZWC bit is set to "0" (writing to the reload register and counter simultaneously), the value is written to each reload register of the TZPR and PREZ registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input. When the TZWC bit is set to "1" (writing to only the reload register), the value is written to each reload register of the TZPR and PREZ registers (the data is transferred to the counter at the following reload).
Item Count Source Count Operation
NOTES: 1. The IR bit in the TZIC register is set to "1" (interrupt requested) when writing to the TZPR or PREZ register while both of the following conditions are met. * TZWC bit in TZMR register is set to "0" (write to reload register and counter simultaneously) * TZS bit in TZMR register is set to "1" (count starts) When writing to the TZPR or PREZ register in the above state, disable an interrupt before writing.
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Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol Address 0080h TZMR Bit Symbol Bit Name -- Reserved Bit (b3-b0) TZMOD0 TZMOD1 TZWC TZS Timer Z Operating Mode Bit Timer Z Write Control Bit(1) Timer Z Count Start Flag(2)
After Reset 00h Function Set to "0"
b5 b4
RW RW RW RW RW RW
0 0 : Timer mode 0 : Write to reload register and counter 1 : Write to reload register only 0 : Stops counting 1 : Starts counting
NOTES : 1. When the TZS bit is set to "1" (count start), the setting value in the TZWC bit is enabled. When the TZWC bit is set to "0", Timer Z count value is w ritten to both reload register and counter. Timer Z count value is w ritten to the reload register only. When the TZS bit is set to "0" (count stop), Timer Z count value is w ritten to both reload register and counter regardless of the setting value in the TZWC bit. 2. Refer to 20.4.3 Tim er Z for precautions on the TZS bit.
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00000000
Symbol Address 0084h PUM Bit Symbol Bit Name -- Reserved Bit (b4-b0) TZOPL INOSTG INOSEG
After Reset 00h Function Set to "0"
RW RW RW RW RW
Timer Z Output Level Latch Set to "0" in timer mode
_____
INT0 Pin One-shot Trigger Control Bit
____
Set to "0" in timer mode Set to "0" in timer mode
INT0 Pin One-shot Trigger Polarity Select Bit
Figure 13.16
TZMR and PUM Registers in Timer Mode
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13.2.2
Programmable Waveform Generation Mode
Programmable waveform generation mode is mode to invert the signal output from the TZOUT pin each time the counter underflows, while the values in the TZPR and TZSC registers are counted alternately (See Table 13.8 Specification of Programmable Waveform Generation Mode). A counting starts by counting the value set in the TZPR register. Figure 13.17 shows TZMR and PUM Registers in Programmable Waveform Generation Mode. Figure 13.18 shows Operating Example of Timer Z in Programmable Waveform Generation Mode. Table 13.8 Specification of Programmable Waveform Generation Mode Specification
f1, f2, f8, Timer X underflow * Decrement * When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Width and Period of Primary period: (n+1)(m+1)/fi Output Waveform Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Count source frequency n: Setting value in PREZ register, m: setting value in TZPR register, p: setting value in TZSC register Count Start Condition Write "1" (count start) to the TZS bit in the TZMR register Count Stop Condition Write "0" (count stop) to the TZS bit in the TZMR register Interrupt Request In half of count source, after Timer Z underflows during secondary period (at the Generation Timing same time as the TZout output change) [Timer Z interrupt] TZOUT Pin Function Pulse output (When using this function as a programmable I/O port, set to timer mode.) INT0 Pin Function Read from timer Write to timer Select function Programmable I/O port, or INT0 interrupt input The count value can be read out by reading the TZPR and PREZ registers(1). The value written to the TZSC, PREZ and TZPR registers is written to the reload register only(2) * Output level latch select function The TZOPL bit can select the output level during primary and secondary periods. * Programmable waveform generation output switch function When the TZOCNT bit in the TZOC register is set to "0", the output from the TZOUT pin is inverted synchronously when Timer Z underflows. And when setting to "1", output the value in the P1_3 bit from the TZOUT pin(3)
Item Count Source Count Operation
NOTES: 1. Even when counting the secondary period, read out the TZPR register. 2. The setting value in the TZPR register and TZSC register are made effective by writing a value to the TZPR register. The set values are reflected to the waveform output beginning with the following primary period after writing to the TZPR register. 3. The TZOCNT bit is enabled by the followings.
* When count starts. * When the timer Z interrupt request is generated. The contents after the TZOCNT bit is changed
are reflected from the output of the following primary period.
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Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1010000
Symbol Address 0080h TZMR Bit Symbol Bit Name Reserved Bit -- (b3-b0) TZMOD0 TZMOD1 TZWC TZS Timer Z Count Start Flag(2) Timer Z Operating Mode Bit Timer Z Write Control Bit
After Reset 00h Function Set to "0"
b5 b4
RW RW RW RW RW RW
0 1 : Programmable Waveform Generation Mode Set to "1" in programmable w aveform generation mode(1) 0 : Stops counting 1 : Starts counting
NOTES : 1. When the TZS bit is set to "1" (count start), The count value is w ritten to the reload register only. When the TZS bit is set to "0" (count stop), The count value is w ritten to both reload register and counter. 2. Refer to 20.4.3 Tim er Z for precautions on the TZS bit.
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
00000
Symbol Address 0084h PUM Bit Symbol Bit Name Reserved Bit -- (b4-b0) Timer Z Output Level Latch
After Reset 00h Function Set to "0" 0 : Outputs Outputs Outputs 1 : Outputs Outputs Outputs "H" for primary period "L" for secondary period "L" w hen the timer is stopped "L" for primary period "H" for secondary period "H" w hen the timer is stopped
RW RW
TZOPL
RW
_____
INOSTG INOSEG
INT0 Pin One-shot Trigger Control Bit
_____
Set to "0" in programmable w aveform generation mode Set to "0" in programmable w aveform generation mode
RW RW
INT0 Pin One-shot Trigger Polarity Select Bit
Figure 13.17
TZMR and PUM Registers in Programmable Waveform Generation Mode
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Set to "1" by program
TZS Bit in TZMR Register
"1" "0"
Count Source
Prescaler Z Underflow Signal
Timer Z secondary reloads Timer Z primary reloads
Contents of Timer Z
01h
00h
02h
01h
00h
01h
00h
02h
Set to "0" when interrupt request is acknowledged, or set by program
IR Bit in TZIC Register
"1" "0"
Set to "0" by program
TZOPL Bit in PUM Register
"1" "0"
Waveform output starts Waveform output inverts Waveform output inverts
TZOUT Pin Output
"H" "L"
Primary period Secondary period Primary period
The above applies to the following conditions. PREZ=01h, TZPR=01h, TZSC=02h TZOC register TZOCNT bit = 0
Figure 13.18
Operating Example of Timer Z in Programmable Waveform Generation Mode
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13.2.3
Programmable One-shot Generation Mode
Programmable one-shot generation mode is mode to output the one-shot pulse from the TZOUT pin by a program or an external trigger input (input to the INT0 pin). (see Table 13.9 Specification of Programmable One-Shot Generation Mode). When a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the TZPR register. The TZSC register is unused in this mode. Figure 13.19 shows the TZMR and PUM Registers in Programmable One-Shot Generation Mode. Figure 13.20 shows an Operating Example in Programmable One-Shot Generation Mode. Table 13.9 Specification of Programmable One-Shot Generation Mode Specification f1, f2, f8, Timer X underflow * Decrement the setting value in the TZPR register * When the timer underflows, it reloads the contents of the reload register before the count completes and the TZOS bit is set to "0" (one-shot stops). * When a count stops, the timer reloads the contents of the reload register before it stops. (n+1)(m+1)/fi fi: Count source frequency, n: setting value in PREZ register, m: setting value in TZPR register
Item Count Source Count Operation
One-Shot Pulse Output Time
Count Start Condition * Set the TZOS bit in the TZOC register to "1" (one-shot starts) (1) * Input active trigger to the INT0 pin(2) Count Stop Condition * When reloading completes after the count value is set to "00h" * When the TZS bit in the TZMR register is set to "0" (count stops) * When the TZOS bit in the TZOC register is set to "0" (one-shot stops) Interrupt Request In half cycles of count source, after the timer underflows (at the same time as the Generation Timing TZOUT output ends) [Timer Z interrupt] TZOUT Pin Function Pulse output (When using this function as a programmable I/O port, set to timer mode.) INT0 Pin Function * When the INOSTG bit in the PUM register is set to "0" (INT0 one-shot trigger disabled) programmable I/O port or INT0 interrupt input * When the INOSTG bit in the PUM register is set to "1" (INT0 one-shot trigger enabled) external trigger (INT0 interrupt input)) The count value can be read out by reading the TZPR and PREZ registers. The value written to the TZPR and PREZ registers is written to the reload register only(3). * Output level latch select function The TZOPL bit can select the output level of the one-shot pulse waveform. * INT0 pin one-shot trigger control and polarity select functions The INOSTG bit can select the trigger input from the INT0 pin is active or inactive. Also, the INOSEG bit can select the active trigger polarity.
Read from Timer Write to Timer Select Function
NOTES: 1. Set the TZS bit in the TZMR register to "1" (count starts). 2. Set the TZS bit to "1" (count starts), the INT0EN bit in the INTEN register to "1" (enables INT0 input), and the INOSTG bit in the PUM register to "1" (INT0 one-shot trigger enabled). A trigger which is input during the count cannot be acknowledged, however the INT0 interrupt request is generated. 3. The set value is reflected at the following one-shot pulse after writing to the TZPR register.
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Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1100000
Symbol Address 0080h TZMR Bit Symbol Bit Name -- Reserved Bit (b3-b0) TZMOD0 TZMOD1 TZWC TZS Timer Z Operating Mode Bit Timer Z Write Control Bit Timer Z Count Start Flag(2)
After Reset 00h Function Set to "0"
b5 b4
RW RW RW RW RW RW
1 0 : Programmable one-shot generation mode Set to "1" in programmable one-shot generation mode(1) 0 : Stops counting 1 : Starts counting
NOTES : 1. When the TZS bit is set to "1" (count start), The count value is w ritten to the reload register only. When the TZS bit is set to "0" (count stop), The count value is w ritten to both reload register and counter. 2. Refer to 20.4.3 Tim er Z for precautions on the TZS bit.
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol Address 0084h PUM Bit Symbol Bit Name -- Reserved Bit (b4-b0)
After Reset 00h Function Set to "0"
RW RW
TZOPL
Timer Z Output Level Latch 0 : Outputs one-shot pulse "H" Outputs "L" w hen the timer is stopped 1 : Outputs one-shot pulse "L" Outputs "H" w hen the timer is stopped
_____ _____
RW
INOSTG INOSEG
INT0 Pin One-shot Trigger Control Bit(1) _____ INT0 Pin One-shot Trigger Polarity Select Bit(2)
0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled 0 : Falling edge trigger 1 : Rising edge trigger
RW RW
NOTES : 1. Set the INOSTG bit to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM _____ register are set. When setting the INOSTG bit to "1" (INT0 pin one-shot trigger enabled), set the INT0F0 to _____ INT0F1 bits in the INT0F register. Set the INOSTG bit to "0" (INT0 pin one-shot trigger disabled) after the TZS bit in the TZMR register is set to "0" (count stop). 2. The INOSEG bit is enabled only w hen the INT0PL bit in the INTEN register is set to "0" (one edge).
Figure 13.19
TZMR and PUM Registers in Programmable One-Shot Generation Mode
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Set to "1" by program
TZS Bit in TZMR Register
"1" "0"
Set to "1" by program Set to "0" when counting ends Set to "1" by INT0 pin input trigger
TZOS Bit in TZOC Register
"1" "0"
Count Source
Prescaler Z Underflow Signal
INT0 Pin Input
"1" "0"
Count starts Timer Z Count primary starts reloads Timer Z primary reloads
Contents of Timer Z
01h
00h
01h
00h
01h
Set to "0" when interrupt request i s acknowledged, or set to "0" by program
IR Bit in TZIC Register
"1" "0"
Set to "0" by program
TZOPL bit in PUM Register
"1" "0"
Waveform output starts Waveform output ends Waveform output starts Waveform output ends
TZOUT Pin Input
"H" "L"
The above applies to the following conditions. PREZ=01h, TZPR=01h TZOPL bit in PUM register=0, INOSTG bit=1 (INT0 one-shot trigger enabled) INOSEG bit=1 (edge trigger at rising edge)
Figure 13.20
Operating Example in Programmable One-Shot Generation Mode
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13. Timers
13.2.4
Programmable Wait One-shot Generation Mode
Programmable wait one-shot generation mode is mode to output the one-shot pulse from the TZOUT pin by the external trigger input (input to the INT0 pin) (see Table 13.10 Specification of Programmable Wait One-Shot Generation Mode Specifications). When a trigger is generated from this point, the timer starts outputting pulses only once for a given length of time equal to the setting value in the TZSC register after waiting for a given length of time equal to the setting value in the TZPR register. Figure 13.21 shows the TZMR and PUM Registers in Programmable Wait OneShot Generation Mode. Figure 13.22 shows an Operating Example in Programmable Wait One-Shot Generation Mode.
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Table 13.10
Specification of Programmable Wait One-Shot Generation Mode Specifications
Specification f1, f2, f8, Timer X underflow * Decrement the setting value in Timer Z primary * When a count of TZPR register underflows, the timer reloads the contents of the TZSC register before the count continues. * When a count of the TZSC register underflows, the timer reloads the contents of the TZPR register before the count completes and the TZOS bit is set to "0". * When a count stops, the timer reloads the contents of the reload register before it stops. Wait Time (n+1)(m+1)/fi fi: Count source frequency n: setting value in PREZ register, m: setting value in TZPR register One-Shot Pulse Output Time (n+1)(p+1)/fi fi: Count source frequency n: setting value in PREZ register, p: setting value in TZSC register Count Start Condition * Set the TZOS bit in the TZOC register to "1" (one-shot starts)(1) * Input active trigger to the INT0 pin(2) Count Stop Condition * When reloading completes after Timer Z underflows during secondary period * When the TZS bit in the TZMR register is set to "0" (count stops) * When the TZOS bit in the TZOC register is set to "0" (one-shot stops) Interrupt Request In half cycles of the count source after Timer Z underflows during Generation Timing secondary period (complete at the same time as waveform output from the TZOUT pin) [timer Z interrupt] TZOUT Pin Function Pulse output (When using this function as a programmable I/O port, set to timer mode.) INT0 Pin Function * When the INOSTG bit in the PUM register is set to "0" (INT0 one-shot trigger disabled), programmable I/O port or INT0 interrupt input * When the INOSTG bit in the PUM register is set to "1" (INT0 one-shot trigger enabled), external trigger (INT0 interrupt input) The count value can be read out by reading the TZPR and PREZ registers. The value written to the TZPR register, PREZ and TZSC register is written to reload register only(3). * Output level latch select function The output level for the one-shot pulse waveform is selected by the TZOPL bit. * INT0 pin one-shot trigger control function and polarity select function Trigger input from the INT0 pin can be set to active or inactive by the INOSTG bit. Also, an active trigger's polarity can be selected by the INOSEG bit.
Item Count Source Count Operation
Read from Timer Write to Timer Select Function
NOTES: 1. Set the TZS bit in the TZMR register to "1" (count starts). 2. Set the TZS bit to "1" (count starts), the INT0EN bit in the INTEN register to "1" (enables INT0 input), and the INOSTG bit in the PUM register to "1" (enabling INT0 one-shot trigger). A trigger which is input during the count cannot be acknowledged, however the INT0 interrupt request is generated. 3. The setting values are reflected beginning with the following one-shot pulse after writing to the TZPR register.
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Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1110000
Symbol Address 0080h TZMR Bit Symbol Bit Name -- Reserved Bit (b3-b0) TZMOD0 TZMOD1 TZWC TZS Timer Z Write Control Bit Timer Z Count Start Flag(2) Timer Z Operating Mode Bit
After Reset 00h Function Set to "0"
b5 b4
RW RW RW RW
1 1 : Programmable w ait one-shot generation mode
Set to "1" in programmable w ait one-shot generation mode(1) 0 : Stops counting 1 : Starts counting
RW RW
NOTES : 1. When the TZS bit is set to "1" (count start), The count value is w ritten to the reload register only. When the TZS bit is set to "0" (count stop), The count value is w ritten to both reload register and counter. 2. Refer to 20.4.3 Tim er Z for precautions on the TZS bit.
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol Address 0084h PUM Bit Symbol Bit Name -- Reserved Bit (b4-b0) Timer Z Output Level Latch TZOPL
_____
After Reset 00h Function Set to "0" 0 : Outputs one-shot pulse "H" Outputs "L" w hen the timer is stopped 1 : Outputs one-shot pulse "L" Outputs "H" w hen the timer is stopped
_____
RW RW
RW
INOSTG INOSEG
INT0 Pin One-shot Trigger Control Bit(1)
_____
INT0 Pin One-shot Trigger Polarity Select Bit(2)
0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled 0 : Falling edge trigger 1 : Rising edge trigger
RW RW
NOTES : 1. Set the INOSTG bit to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM _____ register are set. When setting the INOSTG bit to "1" (INT0 pin one-shot trigger enabled), set the INT0F0 to _____ INT0F1 bits in the INT0F register. Set the INOSTG bit to "0" (INT0 pin one-shot trigger disabled) after the TZS bit in the TZMR register is set to "0" (count stop). 2. The INOSEG bit is enabled only w hen the INT0PL bit in the INTEN register is set to "0" (one edge).
Figure 13.21
TZMR and PUM Registers in Programmable Wait One-Shot Generation Mode
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Set to "1" by program
TZS Bit TZMR Register
"1" "0"
Set to "1" by program, or set to "1" by INT0 pin input trigger Set to "0" when counting ends
TZOS Bit in TZOC Register
"1" "0"
Count Source
Prescaler Z Underflow Signal
INT0 Pin Input
"1" "0"
Count starts Timer Z secondary reloads Timer Z primary reloads
Contents of Timer Z
01h
00h
02h
01h
00h
01h
Set to "0" when interrupt request is accepted, or set by program
IR Bit in TZIC Register
"1" "0"
Set to "0" by program
TZOPL Bit in PUM Register
"1" "0"
Wait starts Waveform output starts Waveform output ends
TZOUT Pin Output
"H" "L"
The above applies to the following conditions. PREZ=01h, TZPR=01h, TZSC=02h PUM register TZOPL bit=0, INOSTG bit=1 (INT0 one-shot trigger enabled) INOSEG bit= 1 (rising edge trigger)
Figure 13.22
Operating Example in Programmable Wait One-Shot Generation Mode
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13.3
Timer C
Timer C is a 16-bit timer. Figure 13.23 shows the Block Diagram of Timer C. Figure 13.24 shows the Block Diagram of CMP Waveform Generation Unit. Figure 13.25 shows the Block Diagram of CMP Waveform Output Unit. Timer C has two modes: input capture mode and output compare mode. Figure 13.26 to 13.29 show the Timer C-associated registers.
TCC11 to TCC10 f1 f8 f32 INT3/TCIN fRING128
=01b =10b =11b Other than 00b =00b
Sampling Clock Digital Filter TCC07=0 TCC07=1 Edge Detection INT3 Interrupt
Transfer Signal Higher 8 Bits Lower 8 Bits
Capture and Compare 0 Register TM0 Register Compare Circuit 0
Data Bus
Compare 0 Interrupt
TCC02 to TCC01 f1 f8 f32 fRING-fast
=00b =01b =10b =11b
Higher 8 bits Counter TYC00 TC register
Lower 8 bits
Timer C Interrupt TCC12=1 Timer C Counter Reset Signal
TCC12 =0
Compare circuit 1
Compare 1 Interrupt
Higher 8 bits
Lower 8 bits
Compare register 1 TM1 register TCC01 to TCC02, TCC07: Bits in TCC0 register TCC10 to TCC12: Bits in TCC1 register
Figure 13.23
Block Diagram of Timer C
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TCC14 TCC15 Compare 0 Interrupt Signal Compare 1 Interrupt Signal TCC16 TCC17 H L Reverse TCC17 to TCC16
=11b =10b =01b D T
Latch
R
Q
CMP Output (internal Signal)
Reset TCC15 to TCC14
=01b =10b =11b
Reverse L H
TCC14 to TCC17: Bits in TCC1 register
Figure 13.24
Block Diagram of CMP Waveform Generation Unit
CMP Output (Internal Signal)
TCOUT6=0 TCOUT0=1 Inverted TCOUT6=1 TCOUT0=0
PD1_0 TCOUT0 CMP0_0
P1_0 Register Bit Setting Value TCOUT TCOUT0 1 1 1 1 P1 P1_0 1 1 0 0 TCOUT TCOUT6 0 1 0 1
CMP0_0 Output CMP0_0 waveform output CMP0_0 reversed waveform output "L" output "H" output
This diagram is a block diagram of the CMP0_0 waveform output unit. The CMP0_1 to CMP0_2 and CMP1_0 to CMP1_2 waveform output units are the same configurations.
Figure 13.25
Block Diagram of CMP Waveform Output Unit
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Timer C Register
(b15) b7 (b8) b0 b7 b0
Symbol TC
Address 0091h-0090h Function
After Reset 0000h RW RO
Counts the internal count source. "0000h" can be read out by reading w hen the TCC00 bit is set to "0" (count stops). Count value can be read out by reading w hen the TCC00 bit is set to "1" (count starts).
Capture and Compare 0 Register
(b15) b7 (b8) b0 b7 b0
Symbol TM0 Mode Input Capture Mode
Address 009Dh-009Ch Function
After Reset 0000h(2) RW RO
When the active edge of measurement pulse is input, store the value in the TC register
Mode Output compare Mode
(1)
Function Store the value compared w ith Timer C
Setting Range 0000h to FFFFh
RW RW
NOTES : 1. When setting the value to the TM0 register, set the TCC13 bit in the TCC1 register to "1" (compare 0 output selected). When the TCC13 bit is set to "0" (capture selected), the value cannot be w ritten. 2. When setting the TCC13 bit in the TCC1 register to "1", the value after reset is "FFFFh".
Compare 1 Register
(b15) b7 (b8) b0 b7 b0
Symbol TM1 Mode Output Compare Mode
Address 009Fh-009Eh Function Store the value compared w ith Timer C
After Reset FFFFh Setting Range 0000h to FFFFh RW RW
Figure 13.26
TC, TM0 and TM1 Registers
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Timer C Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TCC0 Bit Symbol TCC00 TCC01
Address 009Ah Bit Name Timer C Count Start Bit Timer C Count Source Select Bit
(1)
After Reset 00h Function 0 : Stops counting 1 : Starts counting
b2 b1
RW RW RW
TCC02
_____
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fRING-fast INT3 Interrupt / Capture Polarity Select Bit(1, 2)
b4 b3
RW
TCC03
TCC04 -- (b5) Reserved Bit
_____
0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Do not set Set to "0"
_____
RW
RW
RW
TCC06
INT3 Interrupt / Capture Input Bit(2, 3)
0 : INT3 Interrupt is generated synchronizing w ith Timer C count source
_____
_____
TCC07
INT3 Interrupt / Capture Input Sw itch Bit(1, 2)
1 : INT3 Interrupt is generated w hen _____ INT3 interrupt is input(4) _____ 0 : INT3 1 : fRING128
RW
RW
NOTES : 1. Change this bit w hen the TCC00 bit is set to "0" (count stop). 2. The IR bit in the INT3IC register may be set to "1" (requests interrupt) w hen the TCC03, TCC04, TCC06 and TCC07 bits are rew ritten. Refer to 20.2.5 Changing Interrupt Factor.
_____
3. When the TCC13 bit is set to "1" (output compare mode) and INT3 interrupt is input, regardless of the setting value of the TCC06 bit, an interrupt request is generated. _____ _____ 4. When using the INT3 filter, the INT3 interrupt is generated synchronizing w ith the clock for the digital filter.
Figure 13.27
TCC0 Register
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Timer C Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCC1 Bit Symbol TCC10
INT3 Filter Select Bit(1)
_____
Address 009Bh Bit Name
b1 b0
After Reset 00h Function 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW RW
TCC11
RW
TCC12
Timer C Counter Reload Select 0 : No reload 1 : Set TC register to "0000h" w hen compare 1 Bit(3) is matched Compare 0 / Capture Select Bit(2) 0 : Select capture (input capture mode) (3) 1 : Select compare 0 output (output compare mode)
RW
TCC13
RW
TCC14
TCC15
Compare 0 Output Mode Select b5 b4 Bit(3) 0 0 : CMP output remains unchanged even w hen compare 0 matches 0 1 : CMP output is reversed w hen compare 0 signal matches 1 0 : CMP output is set to "L" w hen compare 0 signal matches 1 1 : CMP output is set to "H" w hen compare 0 signal matches Compare 1 Output Mode Select b7 b6 Bit(3) 0 0 : CMP output remains unchanged even w hen compare 1 matches 0 1 : CMP output is reversed w hen compare 1 signal matches 1 0 : CMP output is set to "L" w hen compare 1 signal matches 1 1 : CMP output is set to "H" w hen compare 1 signal matches
RW
TCC16
RW
TCC17
NOTES : _____ 1. When the same value from the INT3 pin is sampled three times continuously, the input is determined. 2. When the TCC00 bit in the TCC0 register is set to "0" (count stops), rew rite the TCC13 bit. 3. When the TCC13 bit is set to "0" (input capture mode), set the TCC12, TCC14 to TCC17 bits to "0".
Figure 13.28
TCC1 Register
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Timer C Output Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCOUT Bit Symbol TCOUT0 TCOUT1 TCOUT2 TCOUT3 TCOUT4 TCOUT5
Address 00FFh Bit Name CMP Output Enable Bit 0 CMP Output Enable Bit 1 CMP Output Enable Bit 2 CMP Output Enable Bit 3 CMP Output Enable Bit 4 CMP Output Enable Bit 5 CMP Output Reverse Bit 0
After Reset 00h Function 0 : Disables CMP output from CMP0_0 1 : Enables CMP output from CMP0_0 0 : Disables CMP output from CMP0_1 1 : Enables CMP output from CMP0_1 0 : Disables CMP output from CMP0_2 1 : Enables CMP output from CMP0_2 0 : Disables CMP output from CMP1_0 1 : Enables CMP output from CMP1_0 0 : Disables CMP output from CMP1_1 1 : Enables CMP output from CMP1_1 0 : Disables CMP output from CMP1_2 1 : Enables CMP output from CMP1_2 0 : Not reverse CMP output from CMP0_0 to CMP0_2 1 : Reverses CMP output from CMP0_0 to CMP0_2
RW RW RW RW RW RW RW
TCOUT6
RW
CMP Output Reverse Bit 1 TCOUT7
0 : Not reverse CMP output from CMP1_0 to CMP1_2 1 : Reverses CMP output from CMP1_0 to CMP1_2
RW
NOTES : 1. Set the bits w hich are not used for the CMP output to "0"
Figure 13.29
TCOUT Register
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13.3.1
Input Capture Mode
Input capture mode is mode to input an edge to the TCIN pin or the fRING128 clock as trigger to latch the timer value and generates an interrupt request. The TCIN input contains a digital filter and this prevents an error caused by noise or so on from occurring. Table 13.11 shows Specification of Input Capture Mode. Figure 13.30 shows an Operating Example in Input Capture Mode. Table 13.11 Specification of Input Capture Mode Specification f1, f8, f32, fRING-fast * Increment * Transfer the value in the TC register to the TM0 register at the active edge of measurement pulse * The value in the TC register is set to "0000h" when the count stops The TCC00 bit in the TCC0 register is set to "1" (count starts) The TCC00 bit in the TCC0 register is set to "0" (count stops) * When the active edge of measurement pulse is input [INT3 interrupt](1) * When Timer C overflows [Timer C interrupt] Programmable I/O port or measurement pulse input (INT3 interrupt input) Programmable I/O port When the TCC00 bit in the TCC0 register is set to "0" (capture disabled) * The count value can be read out by reading the TC register. * The count value at measurement pulse active edge input can be read out by reading the TM0 register Write to the TC and TM0 registers is disabled * INT3/TCIN polarity select function The TCC03 to TCC04 bits can select the active edge of measurement pulse * Digital filter function The TCC11 to TCC10 bits can select the digital filter sampling frequency * Trigger select function The TCC07 bit can select the TCIN input or the fRING128
Item Count Source Count Operation
Count Start Condition Counter Stop Condition Interrupt Request Generation Timing INT3/TCIN Pin Function P1_0 to P1_2, P3_3 to P3_5 Pin Function Counter Value Reset Timing Read from Timer(2)
Write to Timer Select Function
NOTES: 1. The digital filter delay and one count source (max.) delay are generated for the INT3 interrupt. 2. Read the TC and TM0 registers in 16-bit unit.
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FFFFh Overflow
Counter Contents (hex)
Count Starts
Measurement value 2 Measurement value 1
Measurement value 3
0000h Set to "1" by program TCC00 Bit in TCC0 Register "1" "0" The delay caused by digital filter and one count source cycle delay (max.) Measurement Pulse (TCIN Pin Input) "1" "0" Set to "0" by program Period
Transmit (Measurement value 1)
Transmit (Measurement value 2)
Transmit (Measurement value 3)
Transmit Timing from Timer C Counter to TM0 Register
"1" "0" Indeterminate Measurement value 1 Measurement value 3 Indeterminate
TM0 Register
Measurement value 2
Set to "0" when interrupt request is acknowledged, or set by program IR Bit in INT3IC Register "1" "0" Set to "0" when interrupt request is acknowledged, or set by program
IR Bit in TCIC Register
"1" "0"
The above applies to the following conditions. TCC0 register TCC04 to TCC03 bits=01b (capture input polarity is set for falling edge), TCC07=0 (INT3/TCIN input as capture input trigger)
Figure 13.30
Operating Example in Input Capture Mode
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13.3.2
Output Compare Mode
Output compare mode is mode to generate an interrupt request when the value of the TC register matches the value of the TM0 or TM1 register. Table 13.12 shows Specification of Output Compare Mode. Figure 13.31 shows an Operating Example in Output Compare Mode. Table 13.12 Specification of Output Compare Mode Specification f1, f8, f32, fRING-fast * Increment * The value in the TC register is set to "0000h" when a count stops The TCC00 bit in the TCC0 register is set to "1" (count starts) The TCC00 bit in the TCC0 register is set to "0" (count stops) The TCOUT0 to TCOUT5 bits in the TCOUT register is set to "1" (enables CMP output).(2) The TCOUT0 to TCOUT5 bits in the TCOUT register is set to "0" (disables CMP output). * When a match occurs in the compare circuit 0 [compare 0 interrupt] * When a match occurs in the compare circuit 1 [compare 1 interrupt] * When Time C overflows [Timer C interrupt] Programmable I/O port or INT3 interrupt input Programmable I/O port or CMP output(1)
Item Count Source Count Operation Count Start Condition Counter Stop Condition Waveform Output Start Condition Waveform Output Stop Condition Interrupt Request Generation Timing INT3/TCIN Pin Function P1_0 to P1_2 Pins and P3_0 to P3_2 Pins Function Counter Value Reset Timing Read from Timer(1)
When the TCC00 bit in the TCC0 register is set to "0" (count stops) * The value in the compare register can be read out by reading the TM0 and TM1 registers. * The count value can be read out by reading the TC register. * Write to the TC register is disabled. * The values written to the TM0 and TM1 registers are stored in the compare register at the following timings: - When the TM0 and TM1 registers are written if the TCC00 bit is set to "0" (count stops) - When the counter overflows if the TCC00 bit is set to "1" (during counting) and the TCC12 bit in the TCC1 register is set to "0" (free-run) - When the compare 1 matches a counter if the TCC00 bit is set to "1" and the TCC12 bit is set to "1" (set the TC register to "0000h" when the compare 1 matches) * Timer C counter reload select function The TCC12 bit in the TCC1 register can select whether the counter value in the TC register is set to "0000h" when the compare circuit 1 matches or not. * The TCC14 to TCC15 bits in the TCC1 register can select the output level when the compare circuit 0 matches. The TCC16 to TCC17 bits in the TCC1 register can select the output level when the compare circuit 1 matches. * The TCOUT6 to TCOUT7 bits in the TCOUT register can select whether the output is reversed or not.
Write to Timer(1)
Select Function
NOTES: 1. When the corresponding port data is "1", the waveform is output depending on the setting of the registers TCC1 and TCOUT. When the corresponding port data is "0", the fixed level is output (refer to Figure 13.25 Block Diagram of CMP Waveform Output Unit). 2. Access the TC, TM0, and TM1 registers in 16-bit units. Rev.2.10 Jan 19, 2006 REJ09B0164-0210 Page 123 of 253
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Match Set value in TM1 register
Counter content (hex)
Count start Match Set value in TM0 register Match
0000h Time Set to "1" by program TCC00 bit in "1" TCC0 register "0"
Set to "0" when interrupt request is accepted, or set by program
IR bit in CMP0IC "1" register "0" Set to "0" when interrupt request is accepted, or set by program IR bit in CMP1IC "1" register "0"
CMP0_0 output
"1" "0"
"1" CMP1_0 output "0"
Conditions : TCC12 bit in TCC1 register = 1 (TC register is set to "0000h" at Compare 1 match occurrence ) TCC13 bit in TCC1 register = 1 (Compare 0 output selected) TCC15 to TCC14 bits in TCC1 register = 11b (CMP output level is set to high at Compare 0 match occurrence) TCC17 to TCC16 bits in TCC1 register = 10b (CMP output level is set to low at Compare 1 match occurrence) TCOUT6 bit in TCOUT register = 0 (not reversed) TCOUT7 bit in TCOUT register = 1 (reversed) TCOUT0 bit in TCOUT register = 1 (CMP0_0 output enabled) TCOUT3 bit in TCOUT register = 1 (CMP1_0 output enabled) P1_0 bit in P1 register = 1 (high) P3_0 bit in P3 register = 1 (high)
Figure 13.31
Operating Example in Output Compare Mode
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14. Serial Interface
Serial Interface is configured with one channels: UART0. UART0 has an exclusive timer to generate a transfer clock. Figure 14.1 shows a UART0 Block Diagram. Figure 14.2 shows a UART0 Transmit/Receive Unit. UART0 has two modes: clock synchronous serial I/O mode, and clock asynchronous serial I/O mode (UART mode). Figure 14.3 to 14.5 show the UART0-associated registers.
(UART0)
RXD0 CLK1 to CLK0=00b f1 f8 f32
=01b =10b
TXD0 1/16
UART reception Clock synchronous type Reception control circuit Receive clock
CKDIR=0 Internal U0BRG register
1/(n0+1)
External CKDIR=1
1/16
UART transmission Clock synchronous type Transmission control circuit
Transmit clock
Transmit/ receive unit
Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Clock synchronous type (when internal clock is selected)
1/2
CKDIR=0 CKDIR=1
CLK0
CLK polarity reversing circuit
Figure 14.1
UART0 Block Diagram
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1SP
PRYE=0 PAR disabled
Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) UART (7 bits) UART0 receive register
RXD0
SP
2SP
SP
PAR
PAR enabled PRYE=1 UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0 U0RB register
MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7
UART (8 bits) UART (9 bits) Clock synchronous type
D6
D5
D4
D3
D2
D1
D0 U0TB register
2SP
PRYE=1 PAR enabled
UART (9 bits) UART
SP
SP
1SP
PAR
PAR disabled PRYE=0 "0" Clock synchronous type UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits) UART0 transmit register SP: Stop bit PAR: Parity bit
TXD0
Note: Clock synchronous type is provide in UART0 only.
Figure 14.2
UART0 Transmit/Receive Unit
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UART0 Transmit Buffer Register(1, 2)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB
Address 00A3h-00A2h Function
After Reset Indeterminate RW WO --
-- (b8-b0) -- (b15-b9)
Transmit data Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
NOTES : 1. When the transfer data length is 9-bit long, w rite to high-byte data first then low -byte data. 2. Use the MOV instruction to w rite to this register.
UART0 Receive Buffer Register(1)
(b15) b7 (b8) b0 b7 b0
Symbol U0RB Bit Symbol -- (b7-b0) -- (b8) -- (b11-b9) OER FER PER SUM
Address 00A7h-00A6h Bit Name -- --
After Reset Indeterminate Function Receive data (D7 to D0) Receive data (D8) RW RO RO -- RO RO RO RO
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. Overrun Error Flag(2) Framing Error Flag(2) Parity Error Flag(2) Error Sum Flag
(2)
0 : No overrun error 1 : Overrun error 0 : No framing error 1 : Framing error 0 : No parity error 1 : Parity error 0 : No error 1 : Error
NOTES : 1. Read out the UiRB register in 16-bit unit. 2. The SUM, PER, FER and OER bits are set to "0" (no error) w hen the SMD2 to SMD0 bits in the UiMR register are set to "000b" (serial interface disabled) or the RE bit in the U0C1 register is set to "0" (receive disable). The SUM bit is set to "0" (no error) w hen the PER, FER and OER bits are set to "0" (no error). The PER and FER bits are set to "0" even w hen the higher byte of the U0RB register is read out.
UART0 Bit Rate Register(1, 2, 3)
b7 b0
Symbol U0BRG
Address 00A1h Function
After Reset Indeterminate Setting Range 00h to FFh RW WO
Assuming that set value is n, U0BRG divides the count source by n+1 NOTES : 1. Write to this register w hile the serial I/O is neither transmitting nor receiving. 2. Use the MOV instruction to w rite to this register. 3. After setting the CLK0 to CLK1 bits of the U0C0 register, w rite to the U0BRG register.
Figure 14.3
U0TB, U0RB and U0BRG Registers Page 127 of 253
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UART0 Transmit / Receive Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U0MR Bit Symbol SMD0
Address 00A0h Bit Name Serial Interface Mode Select Bit
After Reset 00h Function
b2 b1 b0
RW RW
SMD1
SMD2 CKDIR STPS Internal / External Clock Select Bit Stop Bit Length Select Bit Odd / Even Parity Select Bit PRY Parity Enable Bit Reserved Bit
0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Other than above : Do not set 0 : Internal clock 1 : External clock(1) 0 : 1 Stop Bit 1 : 2 Stop Bits Enables w hen PRYE = 1 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled Set to "0"
RW
RW RW RW
RW
PRYE -- (b7)
RW RW
NOTES : 1. Set the PD1_6 bit in the PD1 register to "0" (input).
UART0 Transmit / Receive Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U0C0 Bit Symbol CLK0
CLK1 -- (b2) TXEPT -- (b4) NCH
Address 00A4h Bit Name BRG Count Source Select b1 b0 0 0 : Selects f1 Bit(1) 0 1 : Selects f8 1 0 : Selects f32 1 1 : Do not set Reserved Bit Transmit Register Empty Flag Set to "0"
After Reset 08h Function
RW RW
RW
RW
0 : Data in transmit register (during transmit) 1 : No data in transmit register (transmit completed)
RO
Nothing is assigned. When w rite, set to "0". When read, its content is "0". Data Output Select Bit CLK Polarity Select Bit 0 : TXD0 pin is a pin of CMOS output 1 : TXD0 pin is a pin of N-channel open drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
-- RW
CKPOL
RW
UFORM
Transfer Format Select Bit 0 : LSB first 1 : MSB first
RW
NOTES : 1. If the BRG count source is sw itched, set the U0BRG register again.
Figure 14.4
U0MR and U0C0 Registers Page 128 of 253
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UART0 Transmit / Receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C1 Bit Symbol TE TI RE RI -- (b7-b4)
Address 00A5h Bit Name Transmit Enable Bit Transmit Buffer Empty Flag Receive Enable Bit Receive Complete Flag(1)
After Reset 02h Function 0 : Disables transmit 1 : Enables transmit 0 : Data in U0TB register 1 : No data in U0TB register 0 : Disables receive 1 : Enables receive 0 : No data in U0RB register 1 : Data in U0RB register
RW RW RO RW RO --
Nothing is assigned. When w rite, set to "0". When read, its content is "0".
NOTES : 1. The RI bit is set to "0" w hen the higher byte of the U0RB register is read out.
UART Transmit / Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0000
0
Symbol UCON Bit Symbol U0IRS -- (b1) U0RRM -- (b6-b3)
Address 00B0h Bit Name UART0 Transmit Interrupt Cause Select Bit Reserved Bit UART0 Continuous Receive Mode Enable Bit Reserved Bit CNTR0 Signal Pin Select Bit(1)
After Reset 00h Function 0 : Transmit buffer empty (TI=1) 1 : Transmit completed (TXEPT=1) Set to "0" 0 : Disables continuous receive mode 1 : Enables continuous receive mode Set to "0" 0 : P1_5/RXD0 _______ P1_7/CNTR00/INT10 ______ 1 : P1_5/RXD0/CNTR01/INT11 P1_7
RW RW RW RW RW
CNTRSEL
RW
NOTES : _____ 1. The CNTRSEL bit selects the input pin of CNTR0 (INTI) signal. When the CNTR0 signal is output, it is output from the CNTR00 pin despite the CNTRSEL bit setting.
Figure 14.5
U0C1 and UCON Registers
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14.1
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode is mode to transmit and receive data using a transfer clock. Table 14.1 lists the Specification of Clock Synchronous Serial I/O Mode. Table 14.2 lists the Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode(1). Table 14.1 Specification of Clock Synchronous Serial I/O Mode Specification * Transfer data length: 8 bits * CKDIR bit in U0MR register is set to "0" (internal clock): fi/(2(n+1)) fi=f1, f8, f32 n=setting value in U0BRG register: 00h to FFh * The CKDIR bit is set to "1" (external clock): input from CLK0 pin * Before transmit starts, the following requirements are required(1) - The TE bit in the U0C1 register is set to "1" (transmit enabled) - The TI bit in the U0C1 register is set to "0" (data in the U0TB register) * Before receive starts, the following requirements are required(1) - The RE bit in the U0C1 register is set to "1" (receive enabled) - The TE bit in the U0C1 register is set to "1" (transmit enabled) - The TI bit in the U0C1 register is set to "0" (data in the U0TB register) * When transmit, one of the following conditions can be selected - The U0IRS bit is set to "0" (transmit buffer empty): when transferring data from the U0TB register to UART0 transmit register (when transmit starts) - The U0IRS bit is set to "1" (transmit completes): when completing transmit data from UARTi transmit register * When receive When transferring data from the UART0 receive register to the U0RB register (when receive completes) * Overrun error(2) This error occurs if serial interface starts receiving the following data before reading the U0RB register and receives the 7th bit of the following data * CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock * LSB first, MSB first selection Whether transmitting or receiving data beginning with the bit 0 or beginning with the bit 7 can be selected * Continuous receive mode selection Receive is enabled immediately by reading the U0RB register
Item Transfer Data Format Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request Generation Timing
Error Detection
Select Function
NOTES: 1. When an external clock is selected, meet the conditions while the CKPOL bit in the U0C0 register is set to "0" (transmit data output at the falling edge and the receive data input at the rising edge of the transfer clock), the external clock is held "H"; if the CKPOL bit in the U0C0 register is set to "1" (transmit data output at the rising edge and the receive data input at the falling edge of the transfer clock), the external clock is held "L". 2. If an overrun error occurs, the value of the U0RB register will be indeterminate. The IR bit in the S0RIC register remains unchanged.
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Table 14.2 Register U0TB U0RB U0BRG U0MR U0C0
Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode(1) Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR CLK1 to CLK0 TXEPT NCH CKPOL UFORM TE TI RE RI U0IRS U0RRM CNTRSEL Set transmit data Receive data can be read Overrun error flag Set bit rate
Set to "001b"
Function
U0C1
UCON
Select the internal clock or external clock Select the count source in the U0BRG register Transmit register empty flag Select TXD0 pin output mode Select the transfer clock polarity Select the LSB first or MSB first Set this bit to "1" to enable transmit/receive Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the factor of UART0 transmit interrupt Set this bit to "1" to use continuous receive mode Set this bit to "1" to select P1_5/RXD0/CNTR01/INT11
NOTES: 1. Set bits which are not in this table to "0" when writing to the registers in clock synchronous serial I/O mode. Table 14.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs "H" level between the operating mode selection of UART0 and transfer start, an "H" (If the NCH bit is set to "1" (the N-channel open-drain output), this pin is in a high-impedance state.) Table 14.3 Pin Name TXD0(P1_4) RXD0(P1_5) I/O Pin Functions in Clock Synchronous Serial I/O Mode Function Output serial data Input serial data Selection Method (Outputs dummy data when performing receive only) PD1_5 bit in PD1 register=0 (P1_5 can be used as an input port when performing transmit only) CKDIR bit in U0MR register=0 CKDIR bit in U0MR register=1 PD1_6 bit in PD1 register=0
CLK0(P1_6)
Output transfer clock Input transfer clock
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* Example of Transmit Timing (when internal clock is selected)
TC
Transfer Clock
TE Bit in U0C1 "1" Register "0" TI Bit in U0C1 Register "1" "0"
Set data to U0TB register
Transfer from U0TB register to UART0 transmit register TCLK Stop pulsing because the TE bit is set to "0"
CLK0
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TXEPT Bit in "1" U0C0 Register "0"
IR Bit in S0TIC "1" Register "0"
Set to "0" when interrupt request is acknowledged, or set by a program
TC=TCLK=2(n+1)/fi fi: frequency of U0BRG count source (f1, f8, f32) The above applies to the following settings: n: setting value to U0BRG register * CKDIR bit in U0MR register = 0 (internal clock) * CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) * U0IRS bit in UCON register = 0 (an interrupt request is generated when the transmit buffer is empty):
* Example of Receive Timing (when external clock is selected)
RE Bit in U0C1 "1" Register "0" TE Bit in U0C1 "1" Register "0" TI Bit in U0C1 Register "1" "0"
1/fEXT Transfer from U0TB register to UART0 transmit register
Write dummy data to U0TB register
CLK0
Receive data is taken in
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
RI Bit in U0C1 "1" Register "0" IR Bit in S0RIC "1" Register "0"
Transfer from UART0 receive register to U0RB register
Read out from U0RB register
Set to "0" when interrupt request is acknowledged, or set by a program
The above applies to the following settings: * CKDIR bit in U0MR register = 1 (external clock) * CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) Meet the following conditions when "H" is applied to the CLK0 pin before receiving data: * TE bit in U0C1 register = 1 (enables transmit) * RE bit in U0C1 register = 1 (enables receive) * Write dummy data to the U0TB register fEXT: frequency of external clock
Figure 14.6
Transmit and Receive Operation
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14.1.1
Polarity Select Function
Figure 14.7 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity.
* When the CKPOL bit in the U0C0 register = 0 (output transmit data at the falling edge and input the receive data at the rising edge of the transfer clock)
CLK0(1)
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
* When the CKPOL bit in the U0C0 register = 1 (output transmit data at the rising edge and input the receive data at the falling edge of the transfer clock)
CLK0(2) TXD0 D0 D1 D2 D3 D4 D5 D6 D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
NOTES : 1. When not transferring, the CLK0 pin level is "H". 2. When not transferring, the CLK0 pin level is "L".
Figure 14.7
Transfer Clock Polarity
14.1.2
LSB First/MSB First Select Function
Figure 14.8 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format.
* When UFORM bit in U0C0 register = 0 (LSB first)(1)
CLK0
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
* When UFORM bit in U0C0 register = 1 (MSB first)(1)
CLK0
TXD0
D7
D6
D5
D4
D3
D2
D1
D0
RXD0
D7
D6
D5
D4
D3
D2
D1
D0
NOTES : 1. The above applies when the CKPOL bit in the U0C0 register is set to "0" (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock).
Figure 14.8
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14. Serial Interface
14.1.3
Continuous Receive Mode
Continuous receive mode is held by setting the U0RRM bit in the UCON register to "1" (enables continuous receive mode). In this mode, reading U0RB register sets the TI bit in the U0C1 register to "0" (data in the U0TB register). When the U0RRM bit is set to "1", do not write dummy data to the U0TB register in a program.
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14. Serial Interface
14.2
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmit and receive data after setting the desired bit rate and transfer data format. Table 14.4 lists the Specification of UART Mode. Table 14.5 lists the Registers to Be Used and Settings in UART Mode. Table 14.4 Specification of UART Mode Specification * Character bit (transfer data): selectable from 7, 8 or 9 bits * Start bit: 1 bit * Parity bit: selectable from odd, even, or none * Stop bit: selectable from 1 or 2 bits * CKDIR bit in U0MR register is set to "0" (internal clock) : fj/(16(n+1)) fj=f1, f8, f32 n=setting value in U0BRG register: 00h to FFh * CKDIR bit is set to "1" (external clock) : fEXT/(16(n+1)) fEXT: input from CLK0 pin n=setting value in U0BRG register: 00h to FFh * Before transmit starts, the following are required - TE bit in U0C1 register is set to "1" (transmit enabled) - TI bit in U0C1 register is set to "0" (data in U0TB register) * Before receive starts, the following are required - RE bit in U0C1 register is set to "1" (receive enabled) - Detects start bit * When transmitting, one of the following conditions can be selected - U0IRS bit is set to "0" (transmit buffer empty): when transferring data from the U0TB register to UART0 transmit register (when transmit starts) - U0IRS bit is set to "1" (transfer ends): when serial interface completes transmitting data from the UART0 transmit register * When receiving When transferring data from the UART0 receive register to U0RB register (when receive ends) * Overrun error(1) This error occurs if serial interface starts receiving the following data before reading the U0RB register and receiving the bit one before the last stop bit of the following data * Framing error This error occurs when the number of stop bits set are not detected * Parity error This error occurs when parity is enabled, the number of 1's in parity and character bits do not match the number of 1's set * Error sum flag This flag is set is set to "1" when any of the overrun, framing, and parity errors is generated
Item Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request Generation Timing
Error Detection
NOTES: 1. If an overrun error occurs, the value in the U0RB register will be indeterminate. The IR bit in the S0RIC register remains unchanged.
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Table 14.5 Register U0TB U0RB U0BRG U0MR
Registers to Be Used and Settings in UART Mode Bit 0 to 8 0 to 8 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 Set transmit data(1) Function Receive data can be read(1) Error flag Set a bit rate Set to "100b" when transfer data is 7-bit long Set to "101b" when transfer data is 8-bit long Set to "110b" when transfer data is 9-bit long Select the internal clock or external clock Select the stop bit Select whether parity is included and odd or even Select the count source for the U0BRG register Transmit register empty flag Select TXD0 pin output mode Set to "0" LSB first or MSB first can be selected when transfer data is 8-bit long. Set to "0" when transfer data is 7- or 9-bit long. Set to "1" to enable transmit Transmit buffer empty flag Set to "1" to enable receive Receive complete flag Select the factor of UART0 transmit interrupt Set to "0" Set to "1" to select P1_5/RXD0/CNTR01/INT11
U0C0
CKDIR STPS PRY, PRYE CLK0, CLK1 TXEPT NCH CKPOL UFORM TE TI RE RI U0IRS, U1IRS U0RRM CNTRSEL
U0C1
UCON
NOTES: 1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7-bit long; bits 0 to 7 when transfer data is 8-bit long; bits 0 to 8 when transfer data is 9-bit long. Table 14.6 lists the I/O Pin Functions in Clock Asynchronous Serial I/O Mode. After the UART0 operating mode is selected, the TXD0 pin outputs "H" level (If the NCH bit is set to "1" (N-channel open-drain outputs), this pin is in a high-impedance state) until transfer starts. Table 14.6 Pin name TXD0(P1_4) RXD0(P1_5) I/O Pin Functions in Clock Asynchronous Serial I/O Mode Function Output serial data Input serial data Selection Method (Cannot be used as a port when performing receive only) PD1_5 bit in PD1 register=0 (P1_5 can be used as an input port when performing transmit only) Programmable I/O Port CKDIR bit in U0MR register=0 Input transfer clock CKDIR bit in U0MR register=1 PD1_6 bit in PD1 register=0
CLK0(P1_6)
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* Transmit Timing When Transfer Data is 8-Bit Long (parity enabled, 1 stop bit)
TC
Transfer Clock
TE Bit in U0C1 "1" Register "0" TI Bit in U0C1 Register "1" "0"
Write data to U0TB register
Transfer from U0TB register to UART0 transmit register Start bit Parity bit Stop bit
Stop pulsing because the TE bit is set to "0"
TXD0
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
"1" TXEPT Bit in U0C0 Register "0"
IR Bit S0TIC Register
"1" "0"
Set to "0" when interrupt request is acknowledged, or set by a program
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT The above timing diagram applies to the following conditions: * PRYE bit in U0MR register = 1 (parity enabled) fj: Frequency of U0BRG count source (f1, f8, f32) * STPS bit in U0MR register = 0 (1 stop bit) fEXT: Frequency of U0BRG count source (external clock) * U0IRS bit in UCON register = 1 (an interrupt request is generated when transmit completes) n: Setting value to U0BRG register
* Transmit Timing When Transfer Data is 9-Bit Long (parity disabled, 2 stop bits)
TC
Transfer Clock
TE Bit in U0C1 "1" Register "0" TI Bit in U0C1 Register "1" "0"
Write data to U0TB register
Transfer from U0TB register to UART0 transmit register Start bit Stop bit Stop bit
TXD0
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
TXEPT Bit in "1" U0C0 Register "0"
IR Bit in S0RIC "1" Register "0" Set to "0" when interrupt request is acknowledged, or set by a program The above timing diagram applies to the following conditions: TC=16 (n + 1) / fj or 16 (n + 1) / fEXT * PRYE bit in U0MR register = 0 (parity disabled) fj: Frequency of U0BRG count source (f1, f8, f32) * STPS bit in U0MR register = 1 (2 stop bits) fEXT: Frequency of U0BRG count source (external clock) * U0IRS bit in UCON register = 0 (an interrupt request is generated when transmit buffer is empty)
n: Setting value to U0BRG register
Figure 14.9
Transmit Timing in UART Mode
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* Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
U0BRG output
U0C1 register RE bit RXD0
"1" "0"
Stop bit Start bit D0 D1 D7
Sampled "L" Transfer clock
Receive data taken in
Reception triggered when transfer clock is generated by falling edge of start bit U0C1 register RI bit S0RIC register RI bit
"1" "0" "1" "0"
Transferred from UART0 receive register to U0RB register
Set to "0" when interrupt request is accepted, or set by a program
The above timing diagram applies to the following conditions. * PRYE bit in U0MR register = 0 (parity disabled) * STPS bit in U0MR register = 0 (1 stop bit)
Figure 14.10
Receive Timing in UART Mode
14.2.1
CNTR0 Pin Select Function
The CNTRSEL bit in the UCON register selects whether P1_7 can be used as the CNTR00/INT10 input pin or P1_5 can be used as the CNTR01/INT11 input pin. When the CNTRSEL bit is set to "0", P1_7 is used as the CNTR00/INT10 pin and when the CNTRSEL bit is set to "1", P1_5 is used as the CNTR01/INT11 pin.
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14.2.2
Bit Rate
Divided-by-16 of frequency by the U0BRG register in UART mode is a bit rate.
* When selecting internal clock Setting value to the U0BRG register = fj Bit Rate x 16 -1
Fj : Count source frequency of the U0BRG register (f1, f8 and f32)
* When selecting external clock Setting value to the U0BRG register = fEXT Bit Rate x 16 -1
fEXT : Count source frequency of the U0BRG register (external clock)
Figure 14.11
Calculation Formula of U0BRG Register Setting Value
Table 14.7 Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200
Bit Rate Setting Example in UART Mode BRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 System Clock = 20MHz System Clock = 8MHz BRG Setting Actual Time BRG Setting Actual Error(%) Error(%) Value (bps) Value Time (bps) 129(81h) 1201.92 0.16 51(33h) 1201.92 0.16 64(40h) 2403.85 0.16 25(19h) 2403.85 0.16 32(20h) 4734.85 -1.36 12(0Ch) 4807.69 0.16 129(81h) 9615.38 0.16 51(33h) 9615.38 0.16 86(56h) 14367.82 -0.22 34(22h) 14285.71 -0.79 64(40h) 19230.77 0.16 25(19h) 19230.77 0.16 42(2Ah) 29069.77 0.94 16(10h) 29411.76 2.12 39(27h) 31250.00 0.00 15(0Fh) 31250.00 0.00 32(20h) 37878.79 -1.36 12(0Ch) 38461.54 0.16 23(17h) 52083.33 1.73 9(09h) 50000.00 -2.34
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15. Clock Synchronous Serial I/O with Chip Select (SSU)
The serial data of the clock synchronous can communicate for the clock synchronous serial I/O with chip select (hereinafter referred to as SSU). Table 15.1 shows a SSU Specification and Figure 15.1 shows a Block Diagram of SSU. Figure 15.2 to 15.8 show SSU Associated Registers. Table 15.1 SSU Specification
Specification * Transfer-data length 8 bits Continuous transmit and receive of serial data are enabled since both transmitter and receiver have buffer structure.(2) Operating Mode * Clock synchronous communication mode * 4-wire bus communication mode (including bidirectional communication) Master / Slave Device Selectable I/O Pin SSCK (I/O) : Clock I/O pin SSI (I/O) : Data I/O pin SSO (I/O) : Data I/O pin SCS (I/O) : Chip-select I/O pin Transfer Clock * When the MSS bit in the SSCRH register is set to "0" (operates as slave device), external clock can be selected. * When the MSS bit in the SSCRH register is set to "1" (operates as master device), internal clock (selects from /256, /128, /64, /32, /16, /8 and /4 and outputs from SSCK pin) can be selected. * Clock polarity and phase of SSCK can be selected. Receive Error Detection * Overrun error Overrun error occurs during receive and completes by error. While the RDRF bit in the SSSR register is set to "1" (data in the SSRDR register) and completing the next serial data receive, the ORER bit is set to "1". Multimaster Error * Conflict error While the SSUMS bit in the SSMR2 register is set to "1" (4-wire bus Detection communication mode) and the MSS bit in the SSCRH register is set to "1" (operates as master device) and when starting a serial communication, the CE bit in the SSSR register is set to "1" if "L" applies to the SCS pin input. When the SSUMS bit in the SSMR2 register is set to "1" (4-wire bus communication mode), the MSS bit in the SSCRH register is set to "0" (operates as slave device) and the SCS pin input changes state from "L" to "H", the CE bit in the SSSR register is set to "1". Interrupt Request 5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full, overrun error and conflict error).(1) Select Function * Data transfer direction Selects MSB-first or LSB-first * SSCK clock polarity Selects "L" or "H" level when clock stops * SSCK clock phase Selects edge of data change and data download NOTES: 1. The interrupt vector table is one of the SSU. 2. When setting to the slave device, do not transmit continuously.
Item Transfer Data Format
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
f1
Internal Clock(f1/i)
Internal Clock Generation Circuit
Multiplexer SSCK SSMR Register SSCRL Register SSCRH Register SCS Transmit / Receive Control Circuit SSER Register SSSR Register SSMR2 Register SSTDR Register
Data Bus
SSO Selector SSI
SSTRSR Register
SSRDR Register
Interrupt Requests (TXI, TEI, RXI, OEI and CEI) i = 4, 8, 16, 32, 64, 128 and 256
Figure 15.1
Block Diagram of SSU
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
SS Control Register H(4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSCRH Bit Symbol CKS0
Address 00B8h Bit Name Transfer Clock Rate Select Bit(1)
After Reset 00h Function
b2 b1 b0
RW RW
CKS1
CKS2 -- (b4-b3) MSS
0 0 0 : f1/256 0 0 1 : f1/128 0 1 0 : f1/64 0 1 1 : f1/32 1 0 0 : f1/16 1 0 1 : f1/8 1 1 0 : f1/4 1 1 1 : Do not set Nothing is assigned. When w rite, set to "0". When read, its content is "0". Master/Slave Device Select Bit(2) Receive Single Stop Bit(3) 0 : Operates as slave device 1 : Operates as master device 0 : Maintains receive operation after receiving 1-byte data 1 : Completes receive operation after receiving 1-byte data
RW
RW
-- RW
RSSTP
RW
-- (b7)
Nothing is assigned. When w rite, set to "0". When read, its content is "0".
--
NOTES : 1. The set clock is used w hen the internal clock is selected. 2. The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to "1" (operates as master device). The MSS bit is set to "0" (operates as slave device) w hen the CE bit in the SSSR register is set to "1" (conflict error occurs). 3. The RSSTP bit is disabled w hen the MSS bit is set to "0" (operates as slave device). 4. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.
Figure 15.2
SSCRH Register
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
SS Control Register L(4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 00B9h SSCRL Bit Symbol Bit Name -- Nothing is assigned. When w rite, set to "0". (b0) When read, its content is "1".
After Reset 01111101b Function RW --
SRES
SSU Control Part Reset When this bit is set to "1", the SSU control part and Bit SSTRSR register are reset. The values of the registers (1) in the SSU register are maintained. Nothing is assigned. When w rite, set to "0". When read, its content is "1". SOL Write Protect Bit(2) The output level can be changed by the SOL bit w hen "0" w hen this bit is set to "0". Writing "1" is disabled. When read, its content is "1". Serial Data Output Value Setting Bit When read, 0 : The last bit of the serial data output is set to "L" 1 : The last bit of the serial data output is set to "H" When w rite,(2,3) 0 : The data outputs "L" after the serial data output 1 : The data outputs "H" after the serial data output
RW
-- (b3-b2) SOLP
--
RW
SOL
RW
-- (b6) -- (b7)
Nothing is assigned. When w rite, set to "0". When read, its content is "1". Nothing is assigned. When w rite, set to "0". When read, its content is "0".
-- --
NOTES : 1. SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR and SSRDR registers. 2. The data output after the serial data is output can be changed w hen w riting to the SOL bit before or after transfer. Set the SOLP bit to "0" and w rite to the SOLP and SOL bits by the MOV instruction w hen w riting to the SOL bit. 3. Do not w rite to the SOL bit during the data transfer. 4. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.
Figure 15.3
SSCRL Register
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
SS Mode Register (2)
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol SSMR Bit Symbol BC0
Address 00BAh Bit Name Bit Counter 2 to 0
After Reset 00011000b Function
b2 b1 b0
RW R
BC1
BC2 -- (b3) -- (b4) Reserved Bit
0 0 0 : 8-bit left 0 0 1 : 1-bit left 0 1 0 : 2-bit left 0 1 1 : 3-bit left 1 0 0 : 4-bit left 1 0 1 : 5-bit left 1 1 0 : 6-bit left 1 1 1 : 7-bit left Set to "1". When read, its content is "1".
R
R
RW --
Nothing is assigned. When w rite, set to "0". When read, its content is "1". SSCK Clock Phase Select Bit
(1)
CPHS
0 : Change data at odd edge (Dow nloads data at even edge) 1 : Change data at even edge (Dow nloads data at odd edge) 0 : "H" w hen clock stops 1 : "L" w hen clock stops 0 : Transfers data at MSB first 1 : Transfers data at LSB first
RW
CPOS MLS
SSCK Clock Polarity Select Bit (1) MSB First/LSB First Select Bit
RW RW
NOTES : 1. Refer to 15.1.1 As sociation betw e en Trans fer Clock Polarity, Phase and Data for the setting of the CPHS and CPOS bits. 2. Refer to 20.6.1 Acce ss Re gisters Ass ociate d w ith SSU for accessing registers associated w ith SSU.
Figure 15.4
SSMR Register
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SS Enable Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSER Bit Symbol
CEIE
Address After Reset 00BBh 00h Bit Name Function Conflict Error Interrupt Enable Bit 0 : Disables conflict error interrupt request 1 : Enables conflict error interrupt request
RW
RW
-- (b2-b1) RE TE
Nothing is assigned. When w rite, set to "0". When read, its content is "0". Receive Enable Bit Transmit Enable Bit Receive Interrupt Enable Bit 0 : Disables receive 1 : Enables receive 0 : Disables transmit 1 : Enables transmit 0 : Disables receive data full and overrun error interrupt request 1 : Enables receive data full and overrun error interrupt request
-- RW RW
RIE
RW
TEIE
Transmit End Interrupt Enable Bit 0 : Disables transmit end interrupt request 1 : Enables transmit end interrupt request
RW
Transmit Interrupt Enable Bit TIE
0 : Disables transmit data empty interrupt request 1 : Enables transmit data empty interrupt request
RW
NOTES : 1. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.
Figure 15.5
SSER Register
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SS Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSSR Bit Symbol CE -- (b1) ORER -- (b4-b3) RDRF
Address 00BCh Bit Name Conflict Error Flag(1)
After Reset 00h Function 0 : No conflict error occurs 1 : Conflict error occurs (2)
RW RW -- RW -- RW
Nothing is assigned. When w rite, set to "0". When read, its content is "0". Overrun Error Flag
(1)
0 : No overrun error occurs 1 : Overrun error occurs (3)
Nothing is assigned. When w rite, set to "0". When read, its content is "0". Receive Data Register Full(1, 4) Transmit End(1, 5) 0 : No data in SSRDR register 1 : Data in SSRDR register 0 : The TDRE bit is set to "0" w hen transmitting the end of the bit in transmit data 1 : The TDRE bit is set to "1" w hen transmitting the end of the bit in transmit data 0 : Data is not transferred from the SSTDR to SSTRSR registers 1 : Data is transferred from the SSTDR to SSTRSR registers
TEND
RW
Transmit Data Empty (1, 5, 6) TDRE
RW
NOTES : 1. When reading "1" and w riting "0", the CE, ORER, RDRF, TEND and TDRE bits are set to "0". 2. When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to "1" (four-w ire bus communication mode) and the MSS bit in the SSCRH register is set to "1" (operates as master _____ device), the CE bit is set to "1" if "L" is applied to the SCS pin input. When the SSUMS bit in the SSMR2 register is set to "1" (four-w ire bus communication mode), the MSS bit in the SSCRH register is set to "0" _____ (operates as slave device) is set to "0" (operates as slave device) and the SCS pin input changes the level from "L" to "H" during transfer, the CE bit is set to "1". 3. Indicates overrun error occurs and receive completes by error w hen receive. When the next serial data receive is completed w hile the RDRF bit is set to "1" (data in the SSRDR register), the ORER bit is set to "1". After the ORER bit is set to "1" (overrun error occurs), do not transmit or receive w hile the ORER bit is set to "1". 4. The RDRF bit is set to "0" w hen reading out the data from the SSRDR register. 5. The TEND and TDRE bits are set to "0" w hen w riting the data to the SSTDR register. 6. The TDRE bit is set to "1" w hen setting the TE bit in the SSER register to "0" (disables transmit). 7. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.
Figure 15.6
SSSR Register
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
SS Mode Register 2(5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSMR2 Bit Symbol SSUMS CSOS SOOS SCKOS
Address 00BDh Bit Name SSU Mode Select Bit(1)
_____
After Reset 00h Function 0 : Clock Synchronous Communication Mode 1 : Four-Wire Bus Communication Mode 0 : CMOS output 1 : NMOS open drain output 0 : CMOS output 1 : NMOS open drain output 0 : CMOS output 1 : NMOS open drain output
b5 b4
RW RW RW RW RW
SCS Pin Open Drain Output Select Bit SSO Pin Open Drain Output Select Bit(1) SSCK Pin Open Drain Output Select Bit SCS Pin Select Bit(2)
_____
CSS0
CSS1 SCKS SSCK Pin Select Bit
0 0 : Functions as port _____ 0 1 : Function as SCS input pin _____ 1 0 : Function as SCS output pin(3) _____ 1 1 : Functions as SCS output pin(3) 0 : Functions as port 1 : Functions as serial clock pin
RW
RW RW
BIDE
Bidirectional Mode Enable Bit(1, 4) 0 : Standard mode (communicates using 2 pins of data input and data output) 1 : Bidirectional mode (communicates using 1 pin of data input and data output)
RW
NOTES : 1. Refer to 15.2 Relationship betw een Data I/O Pin and SS Shift Register for the combination of the data I/O pin. ______ 2. The SCS pin functions as a port, regardless of the contents of the CSS0 and CSS1 bits w hen the SSUMS bit is set to "0" (clock synchronous communication mode). _____ 3. This bit functions as the SCS input pin before starting transfer. 4. The BIDE bit is disabled w hen the SSUMS bit is set to "0" (clock synchronous communication mode). 5. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.
Figure 15.7
SSMR2 Register
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
SS Transmit Data Register (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSTDR
Address 00BEh
After Reset FFh RW
Function Store the transmit data. The stored transmit data is transferred to the SSTRSR register and the transmit is started w hen detecting the SSTRSR register is empty. When the next transmit data is w ritten to the SSTDR register during the data transmit from the SSTRSR register, the data can be transmitted continuously.(1) When the MLS bit in the SSMR register is set to "1" (transfer data w ith LSB-first), the data in w hich MSB and LSB are reversed can be read, after w riting to the SSTDR register. NOTES : 1. When setting to the slave device, do not transmit continuously. 2. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.
RW
SS Receive Data Register (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSRDR
Address 00BFh
After Reset FFh RW
Function Store the receive data.(1) The receive data is transferred to the SSRDR register and the receive operation is completed w hen receiving 1-byte data to the SSTRSR register. At this time, the follow ing receive is possible. The continuous receive is possible by the SSTRSR and SSRDR registers.
RO
NOTES : 1. The SSRDR register maintains the receive data before the overrun error occurs w hen the ORER bit in the SSSR register is set to "1" (overrun error occurs). When an overrun error occurs, the receive data may contain errors and therefore, should be discarded. 2. Refer to 20.6.1 Access Registers Associated w ith SSU for accessing registers associated w ith SSU.
Figure 15.8
SSTDR and SSRDR Register
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.1
Transfer Clock
A transfer clock can be selected from 7 internal clocks (/256, /128, /64, /32, /16, /8 and /4) and an external clock. When using the SSU, set the SCKS bit in the SSMR2 register to "1" and select the SSCK pin as the serial clock pin. When the MSS bit in the SSCRH register is set to "1" (operates as master device), an internal clock can be selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the transfer rate selected in the CKS0 to CKS2 bits in the SSCRH register. When the MSS bit in the SSCRH register is set to "0" (operates as slave device), an external clock can be selected and the SSCK pin functions as input.
15.1.1
Association between Transfer Clock Polarity, Phase and Data
Association between transfer clock polarity, phase and data changes according to a combination of the SSUMS bit in the SSMR2 register and the CPHS and CPOS bits in the SSMR register. Figure 15.9 shows the Association between Transfer Clock Polarity, Phase and Transfer Data. Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register. When the MLS bit is set to "1", transfer is started from the LSB to MSB. When the MLS bit is set to "0", transfer is started from the MSB to LSB.
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
* When SSUMS=0 (clock synchronous communication mode), CPHS bit=0 (data change at odd edge) and CPOS bit=0 ("H" when clock stops)
SSCK
SSO, SSI
b0
b1
b2
b3
b4
b5
b6
b7
* When SSUMS=1 (4-wire bus communication mode) and CPHS=0 (data change at odd edge)
SSCK CPOS=0 ("H" when clock stops) SSCK CPOS=1 ("L" when clock stops) SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7
SCS
* When SSUMS=1 (4-wire bus communication mode), CPHS=1 (data download at odd edge)
SSCK CPOS=0 ("H" when clock stops) SSCK CPOS=1 ("L" when clock stops) SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7
SCS CPHS and CPOS : bits in SSMR register, SSUMS : Bits in SSMR2 register
Figure 15.9
Association between Transfer Clock Polarity, Phase and Transfer Data
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.2
SS Shift Register (SSTRSR)
The SSTRSR register is the shift register to transmit and receive the serial data. When the transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to "0" (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in the SSTRSR register. When the MLS bit is set to "1" (LSB-first), the bit 7 in the SSTDR register is transferred to the bit 0 in the SSTRSR register.
15.2.1
Association between Data I/O Pin and SS Shift Register
Connecting association between the data I/O pin and SSTRSR register (SS shift register) changes according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. Also, connecting association changes according to the BIDE bit in the SSMR2 register. Figure 15.10 shows a Connecting Association between Data I/O Pin and SSTRSR Register.
* When SSUMS=0 (clock synchronous communication mode)
* When SSUMS=1 (4-wire bus communication mode), BIDE=0 (standard mode) and MSS=1 (operates as master device)
SSTRSR Register
SSO
SSTRSR Register
SSO
SSI
SSI
* When SSUMS=1 (4-wire bus communication mode), BIDE=0 (standard mode) and MSS=0 (operates as slave device)
* When SSUMS=1 (4-wire bus communication mode), BIDE=1 (bidirectional mode)
SSTRSR Register
SSO
SSTRSR Register
SSO
SSI
SSI
Figure 15.10
Connecting Association between Data I/O Pin and SSTRSR Register
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.3
Interrupt Requests
SSU has five interrupt requests : transmit data empty, transmit end, receive data full, overrun error and conflict error. Since these interrupt requests are assigned to the SSU interrupt vector table, determining interrupt sources by flags is required. Table 15.2 shows the SSU Interrupt Requests.
Table 15.2 SSU Interrupt Requests
Interrupt Request Transmit Data Empty Transmit End Receive Data Full Overrun Error Conflict Error
Abbreviation TXI TEI RXI OEI CEI
Generation Condition TIE=1, TDRE=1 TEIE=1, TEND=1 RIE=1, RDRF=1 RIE=1, ORER=1 CEIE=1, CE=1
CEIE, RIE, TEIE and TIE : Bits in SSER register ORER, RDRF, TEND and TDRE : Bits in SSSR register Generation conditions of Table 15.2 are met, a SSU interrupt request is generated.Set the each interrupt source to "0" by a SSU interrupt routine. However, the TDRE and TEND bits are automatically set to "0" by writing the transmit data to the SSTDR register and the RDRF bit is automatically set to "0" by reading the SSRDR register. When writing the transmit data to the SSTDR register, at the same time the TDRE bit is set to "1" (data is transmitted from the SSTDR to SSTRSR registers) again and when setting the TDRE bit to "0" (data is not transmitted from the SSTDR to SSTRSR registers), additional 1-byte data may be transmitted.
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.4
Communication Modes and Pin Functions
SSU switches functions of the I/O pin in each communication mode according to the setting of the MSS bit in the SSCRH register and the RE and TE bits in the SSER register. Table 15.3 shows the Association between Communication Modes and I/O Pins.
Table 15.3
Association between Communication Modes and I/O Pins
Communication Mode Clock Synchronous Communication Mode
Bit Setting SSUMS BIDE MSS TE 0 Disabled 0 0 1 1 0 1
RE 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0
SSI Input
-(1) Input Input -(1) Input -(1)
Pin State SSO
-(1) Output
SSCK Input Input Input Output Output Output Input Input Input Output Output Output Input Input Output Output
Output
-(1)
Output Output Input
-(1) Input -(1)
4-Wire Bus Communication Mode
1
0
0
0 1
Output Output Input
-(1) Input -(1) -(1) -(1) -(1)
1
0 1
Output Output Input Output Input Output
1 4-Wire Bus (Bidirectional) Communication Mode(2)
1
0 1
0 1 0 1
NOTES: 1. This pin can be used as programmable I/O port. 2. Do not set both the TE and RE bits to "1" in 4-wire bus (bidirectional) communication mode. SSUMS and BIDE : Bits in SSMR2 register MSS : Bit in SSCRH register TE and RE : Bits in SSER register
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.5 15.5.1
Clock Synchronous Communication Mode Initialization in Clock Synchronous Communication Mode
Figure 15.11 shows an Initialization in Clock Synchronous Communication Mode. Set the TE bit in the SSER register to "0" (disables transmit) and the RE bit to "0" (disables receive) before data transmit / receive as an initialization. When communication mode and format are changed, set the TE bit to "0" and the RE bit to "0" before changing. Setting the RE bit to "0" does not change the contents of the RDRF and ORER flags, and the contents of the SSRDR register.
Start
SSER register
RE bit 0 TE bit 0 SSUMS bit 0
SSMR2 register
SSMR register
CPHS bit 0 CPOS bit 0 Set MLS bit
SSCRH register
Set MSS bit
SSMR2 register
SCKS bit 1 Set SOOS bit
SSCRH register
Set CKS0 to CKS2 bits Set RSSTP bit ORER bit 0(1)
SSSR register
SSER register
RE bit 1 (When receive) TE bit 1 (When transmit) Set RIE, TEIE and TIE bits
End NOTES: 1. Write "0" after reading "1" to set the ORER bit to "0".
Figure 15.11
Initialization in Clock Synchronous Communication Mode
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.5.2
Data Transmit
Figure 15.12 shows an Example of SSU Operation for Data Transmit (Clock Synchronous Communication Mode). During the data transmit, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, it outputs data synchronized with the input clock. When setting the TE bit to "1" (enables transmit) before writing the transmit data to the SSTDR register, the TDRE bit is automatically set to "0" (data is not transferred from the SSTDR to SSTRSR registers) and the data is transferred from the SSTDR to SSTRSR registers. After the TDRE bit is set to "1" (data is transferred from the SSTDR to SSTRSR registers), a transmit is started. When the TIE bit in the SSER register is set to "1", the TXI interrupt request is generated. When one frame of data is transferred while the TDRE bit is set to "0", data is transferred from the SSTDR to SSTRSR registers and a transmit of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to "1", the TEND bit in the SSSR register is set to "1" (the TDRE bit is set to "1" when the last bit of the transmit data is transmitted) and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to "1" (enables transmit-end interrupt request). The SSCK pin is retained "H" after transmit-end. Transmit can not be performed while the ORER bit in the SSRR register is set to "1" (overrun error occurs). Confirm that the ORER bit is set to "0" before transmit. When setting the microcomputer to the slave device, ensure the TEND bit is set to "1" (data transmit ends) and write the following transmit data to the SSTDR register. When setting the microcomputer to the master device, continuous transmit is enabled. Figure 15.13 shows a Sample Flowchart for Data Transmit (Clock Synchronous Communication Mode).
* When SSUMS=0 (clock synchronous communication mode), CPHS=0 (data change at odd numbers) and CPOS=0 ("H" when clock stops)
SSCK
SSO
b0
b1
b7
b0
b1
b7
1 Frame "1" TDRE Bit in SSSR Register "0" "1" TEND Bit in SSSR Register "0" TXI interrupt request generation
1 Frame TEI interrupt request generation
Process by Program
Write data to SSTDR register
Figure 15.12
Example of SSU Operation for Data Transmit (Clock Synchronous Communication Mode)
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE=1 ? Yes
No
(1) After reading the SSSR register and confirming that the TDRE bit is set to "1", write the transmit data to the SSTDR register. When write the transmit data to the SSTDR register, the TDRE bit is automatically set to "0".
Write transmit data to SSTDR register
(2)
Data transmit continued? No
Yes (2)
(2) Determine whether data transmit is continued
(3)
Read TEND bit in SSSR register
(3) When the data transmit is completed, the TEND bit is set to "1". Set the TEND bit to "0" and the TE bit to "0" and complete transmit mode.
TEND=1 ? Yes SSSR register
No
TEND bit 0(1)
SSER register
TE bit 0
End
NOTES: 1. Write "0" after reading "1" to set the TEND bit to "0". 2. When setting the microcomputer to the slave device, ensure the TEND bit is set to "1" (data transmit ends) and write the following transmit data to the SSTDR register. When setting the microcomputer to the master device, continuous transmit is enabled.
Figure 15.13
Sample Flowchart for Data Transmit (Clock Synchronous Communication Mode)
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.5.3
Data Receive
Figure 15.14 shows an Example of Operation for Data Receive (Clock Synchronous Communication Mode). During the data receive, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a salve device, it outputs data synchronized with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts receiving by performing dummy read on the SSRDR register. After the 8-bit data is received, the RDRF bit in the SSSR register is set to "1" (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to "1" (enables RXI and OEI interrupt request), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is automatically set to "0" (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in the SSCRH register to "1" (after receiving 1-byte data, the receive operation is completed). The SSU outputs a clock for receiving 8-bit data and stops. After that, set the RE bit in the SSER register to "0" (disables receive) and the RSSTP bit to "0" (receive operation is continued after receiving the 1-byte data) and read the receive data. If the SSRDR register is read while the RE bit is set to "1" (enables receive), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to "1", the ORER bit in the SSSR register is set to "1" (overrun error occurs : OEI) and the operation is stopped. When the ORER bit is set to "1", receive can not be performed. Confirm that the ORER bit is set to "0" before restarting receive. Figure 15.15 shows a Sample Flowchart for Data Receive (MSS=1) (Clock Synchronous Communication Mode).
* When SSUMS=0 (clock synchronous communication mode), CPHS=0 (data download at even edges) and CPOS bit=0 ("H" when clock stops)
SSCK
SSI
b0
b7
b0 1 Frame
b7
b0
b7
1 Frame RDRF Bit in SSSR Register
"1" "0"
RXI interrupt request generation RXI interrupt request generation RXI interrupt request generation Dummy read in SSRDR register Read data in SSRDR register Read data in SSRDR register
"1" RSSTP Bit in SSCRH Register "0"
Process by program
Set RSSTP bit to "1"
Figure 15.14
Example of Operation for Data Receive (Clock Synchronous Communication Mode)
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
Start
Initialization
(1)
Dummy read on SSRDR register
(1) After setting each register in the SSU register, dummy read on the SSRDR register is performed and receive operation is started. (2) Determine whether the last 1-byte data is received. When the last 1-byte data is received, set to stop after the data is received.
(2)
Last data received? No
Yes
Read ORER bit in SSSR register
Yes (3) ORER=1 ? No Read RDRF bit in SSSR register (3) When a receive error occurs, perform an error (6) process after reading the ORER bit. Then set the ORER bit to "0". Transmit/receive can not be restarted while the ORER bit is set to "1".
(4)
No
RDRF=1 ? Yes
(4) Confirm that the RDRF bit is set to "1". If the RDRF bit is set to "1", read the receive data in the SSRDR register. If the SSRDR register is read, the RDRF bit is automatically set to "0".
Read receive data in SSRDR register
(5)
SSCRH register
RSSTP bit 1
(5)Before the last 1-byte data is received, set the RSSTP bit to "1" and stop after the data is received.
Read ORER bit in SSSR register
(6)
ORER=1 ? No
Yes
Read RDRF in SSSR register
No RDRF=1 ? (7) Yes SSCRH register RSSTP bit 0
(7) Confirm that the RDRF bit is set to "1". When the receive operation is completed, set the RSSTP bit to "0" and the RE bit to "0" before reading the last 1byte data. If the SSRDR register is read before setting the RE bit to "0", the receive operation is restarted again. Overrun error process
SSER register
RE bit 0
Read receive data in SSRDR register
End
Figure 15.15
Sample Flowchart for Data Receive (MSS=1) (Clock Synchronous Communication Mode)
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.5.4
Data Transmit/Receive
Data transmit/receive is a combined operation of data transmit and receive which are described before. Transmit/receive is started by writing data in the SSTDR register. When the 8th clock rises or the ORER bit is set to "1" (overrun error occurs) while the TDRE bit is set to "1" (data is transferred from the SSTDR to SSTRSR registers), the transmit/receive operation is stopped. When switching from transmit mode (TE=1) or receive mode (RE=1) to transmit/receive mode (Te=RE=1), set the TE bit to "0" and RE bit to "0" before switching. After confirming that the TEND bit is set to "0" (the TDRE bit is set to "0" when the last bit of the transmit data is transmitted), the RERF bit is set to "0" (no data in the SSRDR register) and the ORER bit is set to "0" (no overrun error), set the TE and RE bits to "1". When setting the microcomputer to the slave device, ensure the TEND bit is set to "1" (data transmit ends) and write the following transmit data to the SSTDR register. When setting the microcomputer to the master device, continuous transmit is enabled. Figure 15.16 shows a Sample Flowchart for Data Transmit/Receive (Clock Synchronous Communication Mode).
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE=1 ? Yes
No
(1) After reading the SSSR register and confirming that the TDRE bit is set to "1", write the transmit data in the SSTDR register. When writing the transmit data to the SSTDR register, the TDRE bit is automatically set to "0".
Write transmit data to SSTDR register
(2)
Read RDRF bit in SSSR register
No RDRF=1 ? Yes Read receive data in SSRDR register
(2) Confirm that the RDRF bit is set to "1". If the RDRF bit is set to "1", read the receive data in the SSRDR register. When reading the SSRDR register, the RDRF bit is automatically set to "0".
(3)
Data transmit continued? No
Yes
(3) Determine whether the transmit data is continued.
(4)
Read TEND bit in SSSR register
(4) When the data transmit is completed, the TEND bit in the SSSR register is set to "1".
TEND=1 ? Yes (5) SSSR register
No
TEND bit 0(1)
(5) Set the TEND bit to "0" and the RE and TE bits in (6) the SSER register to "0" before ending transmit/ receive mode.
(6)
SSER register
RE bit 0 TE bit 0
End
NOTES: 1. Write "0" after reading "1" to set the TEND bit to "0".
Figure 15.16
Sample Flowchart for Data Transmit/Receive (Clock Synchronous Communication Mode)
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.6
Operation in 4-Wire Bus Communication Mode
4-wire bus communication mode is a mode which communicates with the 4-wire bus; a clock line, data input line, data output line and chip select line. This mode includes bidirectional mode in which the data input line and data output line function as a single pin. The data input line and output line are changed according to the setting of the MSS bit in the SSCRH register and the BIDE bit in the SSMR2 register. For details, refer to 15.2.1 Association between Data I/O Pin and SS Shift Register. In this mode, association between the clock polarity, phase and data can be set by the CPOS and CPHS bits in the SSMR register. For details, refer to 15.1.1 Association between Transfer Clock Polarity, Phase and Data. When the SSU is set as a master device, the chip select line controls output. When the SSU is set as a slave device, the chip select line controls input. When the SSU is set as master device, the chip select line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in the SSMR2 register. When the SSU is set as a slave device, the chip select line set the SCS pin as an input pin by setting the CSS1 and CSS0 bits in the SSMR2 register to "01b". In 4-wire bus communication mode, the MLS bit in the SSMR register is set to "0" and communication is performed using the MSB-first.
15.6.1
Initialization in 4-Wire Bus Communication Mode
Figure 15.17 shows an Initialization in 4-Wire Bus Communication Mode. Before the data transit/ receive, set the TE bit in the SSER register to "0" (disables transmit) and the RE bit in the SSER register to "0" (disables receive) and initialize the SSU. When communication mode and format are changed, set the TE bit to "0" and the RE bit to "0" before changing. Setting the RE bit to "0" does not change the contents of the RDRF and ORER flags, and the contents of the SSRDR register.
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
Start
SSER register
RE bit 0 TE bit 0 SSUMS bit 1
SSMR2 register
(1)
SSMR register
Set CPHS and CPOS bits MLS bits 0
(1) The MLS bit is set to "0" for the MSB-first transfer. The clock polarity and phase are set by the CPHS and CPOS bits.
SSCRH register
Set MSS bit (2) Set the BIDE bit to "1" in bidirectional mode and the I/O of the #SCS pin is set by the CSSO to CSS1 bits.
SSMR2 register (2)
SCKS bit 1 Set SOOS, CSS to CSS1 and BIDE bits
SSCRH register
Set CKS0 to CKS2 bits
SSSR register
ORER bit 0(1)
SSCRH register
Set RSSTP bit
SSER register
RE bit 1 (when receive) TE bit 1 (when transmit) Set RIE, TEIE and TIE bits
End
NOTES: 1. Write "0" after reading "1" to set the ORER bit to "0".
Figure 15.17
Initialization in 4-Wire Bus Communication Mode
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.6.2
Data Transmit
Figure 15.18 shows an Example of Operation in Data Transmit (4-Wire Bus Communication Mode). During the data transmit, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the UUSA is set as a slave device, it outputs data in synchronized with the input clock while "L" applies to the SCS pin. When writing the transmit data to the SSTDR register after setting the TE bit to "1" (enables transmit), the TDRE bit is automatically set to "0" (data is not transferred from the SSTDR to SSTRSR registers) and the data is transferred from the SSTDR to SSTRSR registers. After the TDRE bit is set to "1" (data is transferred from the SSTDR to SSTRSR registers), a transmit is started. When the TIE bit in the SSER register is set to "1", the TXI interrupt request is generated. When the 1-frame data is transferred while the TDRE bit is set to "0", the data is transferred from the SSTDR to SSTRSR registers and the next frame transmit is started. If the 8th bit is transmitted while the TDRE is set to "1", the TEND in the SSSR register is set to "1" (when the last bit of the transmit data is transmitted, the TDRE bit is set to "1") and the state is retained. If the TEIE bit in the SSER register is set to "1" (enables transmit-end interrupt request), the TEI interrupt request is generated. The SSCK pin is retained "H" after transmit-end and the SCS pin is held "H". When the SCS pin is transmitted When transmitting continuously while the SCS pin is held "L", write the next transmit data to the SSTDR register before transmitting the 8th bit. Transmit can not be performed while the ORER bit in the SSSR register is set to "1" (overrun error occurs). Confirm that the ORER bit is set to "0" before transmit. When setting the microcomputer to the slave device, ensure the TEND bit is set to "1" (data transmit ends) and write the following transmit data to the SSTDR register. When setting the microcomputer to the master device, continuous transmit is enabled. The difference from the clock synchronous communication mode is that the SSO pin is placed in high-impedance state while the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in high-impedance state while the SCS pin is placed in "H" input state when operating as a slave device. A sample flowchart is the same as the clock synchronous communication mode (Refer to Figure 15.13 Sample Flowchart for Data Transmit (Clock Synchronous Communication Mode)).
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
* When CPHS bit=0 (data change at even edges), CPOS bit=0 ("H" when clock stops)
High-Impedance SCS (Output)
SSCK
SSO
b7
b6 1 Frame
b0
b7
b6 1 Frame
b0
TDRE Bit in SSSR Register
"1" "0" "1" "0"
Data write to SSTDR register TXI interrupt request is generated TEI interrupt request is generated TXI interrupt request is generated
TEND Bit in SSSR Register
Process by Program
* When CPHS bit=1 (data change at even edges), CPOS bit=0 ("H" when clock stops)
High-Impedance SCS (Output) SSCK
SSO
b7
b6 1 Frame
b0
b7 1 Frame
b6
b0
TDRE Bit in SSSR Register
"1" "0" "1" "0"
Data write to SSTDR register TXI interrupt request is generated TEI interrupt request is generated TXI interrupt request is generated
TEND Bit in SSSR Register
Process by Program
CPHS, CPOS : Bits in SSMR register
Figure 15.18
Example of Operation in Data Transmit (4-Wire Bus Communication Mode)
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.6.3
Data Receive
Figure 15.19 shows an example of the SSU operation for the data receive. During the data receive, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a salve device, it outputs data synchronized with the input clock while the SCS pin is held "L" input. When the SSU is set as a master device, it outputs a receive clock and starts receiving by performing dummy read on the SSRDR register. After the 8-bit data is received, the RDRF bit in the SSSR register is set to "1" (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to "1" (enables RXI and OEI interrupt request), the RXI interrupt request is generated. If the SSRDR register is read, the RDRF bit is automatically set to "0" (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in the SSCRH register to "1" (after receiving 1-byte data, the receive operation is completed). The SSU outputs a clock for receiving 8-bit data and stops. After that, set the RE bit in the SSER register to "0" (disables receive) and the RSSTP bit to "0" (receive operation is continued after receiving 1-byte data) and read the receive data. If the SSRDR register is read while the RE bit is set to "1" (enables receive), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to "1", the ORER bit in the SSSR register is set to "1" (overrun error occurs : OEI) and the operation is stopped. When the ORER bit is set to "1", receive can not be performed. Confirm that the ORER bit is set to "0" before restarting receive. When the RDRF and ORER bits are set to "1", it varies depending on setting the CPHS bit in the SSMR register. Figure 15.19 shows when the RDRF and ORER bits are set to "1". When the CPHS bit is set to "1" (data download at the odd edges), the RDRF and ORER bits are set to "1" at one point of a frame. A sample flowchart is the same as the clock synchronous communication mode (Refer to Figure 15.15 Sample Flowchart for Data Receive (MSS=1) (Clock Synchronous Communication Mode)).
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
* When CPHS bit=0 (data download at even edges) and CPOS bit=0 ("H" when clock stops)
SCS (Output) High-Impedance
SSCK
SSI
b7 1 Frame
b0
b7 1 Frame
b0
b7
b0
RDRF Bit in SSSR Register
"1" "0" "1" "0"
Dummy read in SSRDR register Data read in SSRDR register Set RSSTP bit to "1" RXI interrupt request is generated RXI interrupt request is generated
RSSTP Bit in SSCRH Register
RXI interrupt request is generated
Process by Program
Data read in SSRDR register
* When CPHS bit=1 (data download at odd edges) and CPOS bit=0 ("H" when clock stops)
High-Impedance SCS (Output) SSCK
SSI
b7 1 Frame
b0
b7 1 Frame
b0
b7
b0
RDRF Bit in SSSR Register
"1" "0" "1" "0"
Dummy read in SSRDR register Data read in SSRDR register Set RSSTP bit to "1" RXI interrupt request is generated RXI interrupt request is generated
RSSTP Bit in SSCRH Register
RXI interrupt request is generated
Process by Program
Data read in SSRDR register
CPHS and CPOS : Bit in SSMR register
Figure 15.19
Example of Operation in Data Receive (4-Wire Bus Communication Mode)
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15. Clock Synchronous Serial I/O with Chip Select (SSU)
15.6.4
SCS Pin Control and Arbitration
When setting the SSUMS bit in the SSMR2 register to "1" (4-wire bus communication mode).and the CSS1 bit in the SSMR2 register to "1" (functions as SCS output pin), Set the MSS bit in the SSCRH register to "1" (operates as a master device) and check the arbitration of the SCS pin before starting serial transfer. If the SSU detects that the synchronized internal SCS signal is held "L" in this period, the CE bit in the SSSR register to "1" (a conflict error occurs) and the MSS bit is automatically set to "0" (operates as a slave device). Figure 15.20 shows an Arbitration Check Timing. A future transmit operation is not performed while the CE bit is set to "1". Set the CE bit to "0" (a conflict error does not occur) before a transmit is started.
SCS Input
Internal SCS (Synchronization) MSS Bit in SSCRH Register "1" "0"
Transfer Start
CE
Data Write to SSTDR Register
High-Impedance SCS Output Maximum Time of SCS Internal Synchronization
During Arbitration Detection
Figure 15.20
Arbitration Check Timing
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16. A/D Converter
16. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares the pins with P1_0 to P1_3. Therefore, when using these pins, ensure the corresponding port direction bits are set to "0" (input mode). When not using the A/D converter, set the VCUT bit in the ADCON1 register to "0" (Vref unconnected), so that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. The result of A/D conversion is stored in the AD register. Table 16.1 lists the Performance of A/D converter. Figure 16.1 shows the Block Diagram of A/D Converter. Figures 16.2 and 16.3 show the A/D converter-related registers.
Table 16.1 Performance of A/D converter
Item A/D Conversion Method Analog Input Voltage(1) Operating Clock AD(2) Resolution Absolute Accuracy
Performance Successive approximation (with capacitive coupling amplifier) 0V to Vref 4.2V AVCC 5.5V f1, f2, f4 2.7V AVCC < 4.2V f2, f4 8 bit or 10 bit is selectable AVCC = Vref = 5V * 8-bit resolution 2 LSB * 10-bit resolution 3 LSB AVCC = Vref = 3.3 V * 8-bit resolution 2 LSB * 10-bit resolution 5 LSB
Operating Mode
One-shot and repeat modes(3) Analog Input Pin 4 pins (AN8 to AN11) A/D Conversion Start Condition * Software trigger Set the ADST bit in the ADCON0 register to "1" (A/D conversion starts) * Capture Timer Z interrupt request is generated while the ADST bit is set to "1" Conversion Rate Per Pin * Without sample and hold function 8-bit resolution: 49AD cycles, 10-bit resolution: 59AD cycles * With sample and hold function 8-bit resolution: 28AD cycles, 10-bit resolution: 33AD cycles
NOTES: 1. Analog input voltage does not depend on use of sample and hold function. 2. The frequency of AD must be 10 MHz or below. Without sample and hold function, the AD frequency should be 250 kHz or above. With the sample and hold function, the AD frequency should be 1 MHz or above. 3. In repeat mode, only 8-bit mode can be used.
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16. A/D Converter
A/D Conversion Rate Selection f1
CKS0=1 CKS1=1
f2 f4
CKS0=0 VCUT=0 CKS1=0
AD
AVSS VREF
VCUT=1
Resistor Ladder
Successive Conversion Register
Software Trigger Timer Z Interrupt Request
ADCAP=0
ADCON0
Trigger
ADCAP=1 Vcom
AD Register
Decoder Comparator
Data Bus
ADGSEL0=0
VIN
ADGSEL0=1
P1_0/AN8 P1_1/AN9 P1_2/AN10 P1_3/AN11
CH2 to CH0=100b CH2 to CH0=101b CH2 to CH0=110b CH2 to CH0=111b
CH0 to CH2, CKS0 : Bits in ADCON0 register CKS1, VCUT: Bits in ADCON1 register
Figure 16.1
Block Diagram of A/D Converter
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16. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0 ADCAP ADST
Address 00D6h Bit Name Analog Input Pin Select Bit(2)
After Reset 00000XXXb Function
b2 b1 b0
RW RW RW RW RW RW RW RW
1 0 0 : AN8 1 0 1 : AN9 1 1 0 : AN10 1 1 1 : AN11 Other than above : Do not set
A/D Operation Mode Select 0 : On-shot mode Bit(3) 1 : Repeat mode A/D Input Group Select Bit 0 : Disabled 1 : Enabled (AN8 to AN11)
A/D Conversion Automatic 0 : Starts in softw are trigger (ADST bit) Start Bit 1 : Starts in capture (Requests Timer Z interrupt) A/D Conversion Start Flag Frequency Select Bit 0 0 : Disabes A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1(4) 1 : Do not set
CKS0
RW
NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is indeterminate. 2. CH0 to CH2 bits are enabled w hen the ADGSEL0 bit is set to "1". After setting the ADGSEL0 bit to "1", w rite to the CH0 to CH2 bits. 3. When changing A/D operatio mode, set the analog input pin again. 4. Set oAD frequency to 10MHz or below .
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
000
Symbol Address 00D7h ADCON1 Bit Symbol Bit Name -- Reserved Bit (b2-b0) BITS CKS1 VCUT -- (b6-b7) 8/10-bit Mode Select Bit(2) Frequency Select Bit 1 Vref Connect Bit(3) Reserved Bit
After Reset 00h Function Set to "0" 0 : 8-bit mode 1 : 10-bit mode Refer to a description of the CKS0 bit in the ADCON0 register function 0 : Vref not connected 1 : Vref connected Set to "0"
RW RW RW RW RW RW
NOTES : 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is indeterminate. 2. Set the BITS bit to "0" (8-bit mode) in repeat mode. 3. When the VCUT bit is set to "1"(connected) from "0" (not connected), w ait for 1s or more before starting A/D conversion.
Figure 16.2
ADCON0 and ADCON1 Registers
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16. A/D Converter
A/D Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol ADCON2 Bit Symbol SMP -- (b3-b1) -- (b7-b4)
Address 00D4h Bit Name A/D Conversion Method Select Bit Reserved Bit
After Reset 00h Function 0 : Without sample and hold 1 : With sample and hold Set to "0"
RW RW RW --
Nothing is assigned. When w rite, set to "0". When read, its content is "0".
NOTES : 1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result is indeterminate.
A/D Register
(b15) b7 (b8) b0 b7 b0
Symbol AD Function When BITS bit in ADCON1 register is set to "1" (10-bit mode). 8 low -order bits in A/D conversion result 2 high-order bits in A/D conversion result Nothing is assigned. When w rite, set to "0". When read, its content is "0".
Address 00C1h-00C0h
After Reset Indeterminate
When BITS bit in ADCON1 register is set to "0" (8-bit mode). A/D conversion result When read, its content is indeterminate.
RW
RO RO --
Figure 16.3
ADCON2 and AD Registers
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16. A/D Converter
16.1
One-Shot Mode
In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 16.2 lists the Specification of One-Shot Mode. Figure 16.4 shows the ADCON0 and ADCON1 Registers in One-Shot Mode.
Table 16.2 Specification of One-Shot Mode
Item Function Start Condition
Stop Condition Interrupt Request Generation Timing Input Pin Reading of A/D Conversion Result
Specification The input voltage on one selected pin by the CH2 to CH0 bits is A/D converted once * When the ADCAP bit is set to "0" (software trigger), set the ADST bit to "1" (A-D conversion starts) * When the ADCAP bit is set to "1" (capture), Timer Z interrupt request is generated while the ADST bit is set to "1" * A/D conversion completes (ADST bit is set to "0") * Set the ADST bit to "0" A/D conversion completes Select one of AN8 to AN11 Read AD register
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16. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
101
Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0 ADCAP ADST
Address 00D6h Bit Name Analog Input Pin Select Bit(2)
After Reset 00000XXXb Function
b2 b1 b0
RW RW RW RW RW RW RW RW
1 0 0 : AN8 1 0 1 : AN9 1 1 0 : AN10 1 1 1 : AN11 Other than above : Do not set
A/D Operation Mode Select 0 : One-shot mode Bit(3) A/D Input Group Select Bit 0 : Disabled 1 : Enabled (AN8 to AN11)
A/D Conversion Automatic 0 : Starts in softw are trigger (ADST bit) Start Bit 1 : Starts in capture (requests Timer Z interrupt) A/D Conversion Start Flag Frequency Select Bit 0 0 : Disables A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1(4) 1 : Do not set
CKS0
RW
NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is indeterminate. 2. CH0 to CH2 bits are enabled w hen the ADGSEL0 bit is set to "1". After setting the ADGSEL0 bit to "1", w rite to the CH0 to CH2 bits. 3. When changing A/D operation mode, set the analog input pin again. 4. Set oAD frequency to 10MHz or below .
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
001
000
Symbol Address 00D7h ADCON1 Bit Symbol Bit Name -- Reserved Bit (b2-b0) BITS CKS1 VCUT -- (b6-b7) 8/10-bit Mode Select Bit Frequency Select Bit 1 Vref Connect Bit(2) Reserved Bit
After Reset 00h Function Set to "0" 0 : 8-bit mode 1 : 10-bit mode Refer to a description of the CKS0 bit in the ADCON0 register function 1 : Vref connected Set to "0"
RW RW RW RW RW RW
NOTES : 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is indeterminate. 2. When the VCUT bit is set to "1"(connected) from "0" (not connected), w ait for 1s or more before starting A/D conversion.
Figure 16.4
ADCON0 and ADCON1 Registers in One-Shot Mode
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16. A/D Converter
16.2
Repeat Mode
In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 16.3 lists the Repeat Mode Specifications. Figure 16.5 shows the ADCON0 and ADCON1 Registers in Repeat Mode.
Table 16.3 Repeat Mode Specifications
Specification Function The Input voltage on one pin selected by CH2 to CH0 and ADGSEL0 bits is A/D converted repeatedly Start condition * When the ADCAP bit is set to "0" (software trigger) Set the ADST bit to "1" (A-D conversion starts) * When the ADCAP bit is set to "1" (capture) Timer Z interrupt request is generated while the ADST bit is set to "1" Stop condition Set the ADST bit to "0" Interrupt request generation Not generated timing Input pin Select one of AN8 to AN11 Reading of result of A/D Read AD register converter
Item
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16. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
111
Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0 ADCAP ADST
Address 00D6h Bit Name Analog Input Pin Select Bit(2)
After Reset 00000XXXb Function
b2 b1 b0
RW RW RW RW RW RW RW RW
1 0 0 : AN8 1 0 1 : AN9 1 1 0 : AN10 1 1 1 : AN11 Other than above : Do not set
A/D Operating Mode Select 1 : Repeat mode Bit(3) A/D Input Group Select Bit 0 : Disabled 1 : Enabled (AN8 to AN11)
A/D Conversion Automatic 0 : Starts in softw are trigger (ADST bit) Start Bit 1 : Starts in capture (requests Timer Z interrupt) A/D Conversion Start Flag Frequency Select Bit 0 0 : Disables A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1(4) 1 : Do not set
CKS0
RW
NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is indeterminate. 2. CH0 to CH2 bits are enabled w hen the ADGSEL0 bit is set to "1". After setting the ADGSEL0 bit to "1", w rite to the CH0 to CH2 bits. 3. When changing A/D operating mode, set the analog input pin again. 4. Set oAD frequency to 10MHz or below .
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
001
0000
Symbol Address 00D7h ADCON1 Bit Symbol Bit Name -- Reserved Bit (b2-b0) BITS CKS1 VCUT -- (b6-b7) 8/10-bit Mode Select Bit(2) Frequency Select Bit 1 Vref Connect Bit(3) Reserved Bit
After Reset 00h Function Set to "0" 0 : 8-bit mode Refer to a description of the CKS0 bit in the ADCON0 register function 1 : Vref connected Set to "0"
RW RW RW RW RW RW
NOTES : 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is indeterminate. 2. Set the BITS bit to "0" (8-bit mode) in repeat mode. 3. When the VCUT bit is set to "1"(connected) from "0" (not connected), w ait for 1s or more before starting A/D conversion.
Figure 16.5
ADCON0 and ADCON1 Registers in Repeat Mode
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16. A/D Converter
16.3
Sample and Hold
When the SMP bit in the ADCON2 register is set to "1" (with sample and hold function), A/D conversion rate per pin increases to 28AD cycles for 8-bit resolution or 33AD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold circuit is to be used or not. When performing the A/D conversion, charge the comparator capacitor in the microcomputer. Figure 16.6 shows the Timing Diagram of A/D Conversion.
Sample & Hold Disabled
Conversion time at the 1st bit Sampling Time 4o AD cycle
at the 2nd bit
Comparison Sampling Time Comparison Sampling Time Comparison 2.5o AD cycle 2.5o AD cycle Time Time Time
* Repeat until conversion ends
Sample & Hold Enabled
Conversion time at the 1st bit Sampling Time 4o AD cycle Comparison Time
at the 2nd bit Comparison Comparison Comparison Time Time Time
* Repeat until conversion ends
Figure 16.6
Timing Diagram of A/D Conversion
16.4
A/D Conversion Cycles
Figure 16.7 shows the A/D Conversion Cycles.
Conversion time at the 1st bit
Conversion time at the 2nd bit and the follows
End process
A/D Conversion Mode Without Sample & Hold Without Sample & Hold With Sample & Hold With Sample & Hold 8 bits 10 bits 8 bits 10 bits
Conversion Time 49AD 59AD 28AD 33AD
Sampling Time 4AD 4AD 4AD 4AD
Comparison Time 2.0AD 2.0AD 2.5AD 2.5AD
Sampling Time 2.5AD 2.5AD 0.0AD 0.0AD
Comparison End process Time 2.5AD 2.5AD 2.5AD 2.5AD 8.0AD 8.0AD 4.0AD 4.0AD
Figure 16.7
A/D Conversion Cycles
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16. A/D Converter
16.5
Internal Equivalent Circuit of Analog Input
Figure 16.8 shows the Internal Equivalent Circuit of Analog Input.
VCC VCC VSS AVCC Parasitic Diode AN8 ON Resistor Approx. 2k Wiring Resistor Approx. 0.2k SW1 Parasitic Diode ON Resistor Approx. 0.6k Analog Input Voltage SW2 VIN ON Resistor Approx. 5k SW3
C = Approx.1.5pF
AMP
Sampling Control Signal VSS
SW4
i=4
i Ladder-type Switches
i Ladder-type Wiring Resistors AVSS
Chopper-type Amplifier
ON Resistor Approx. 2k Wiring Resistor Approx. 0.2k AN11 SW1
b2 b1 b0 A/D Control Register 0
VREF
Reference Control Signal
A/D Successive Conversion Register
Vref
Resistor ladder
AVSS
SW2
ON Resistor Approx. 0.6k f
Comparison voltage A/D Conversion Interrupt Request
Comparison reference voltage (Vref) generator
Sampling C parison om C onnect to
SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A/D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left.
Control signal for SW2
C onnect to
C onnect to
SW4 conducts only when A/D conversion is not in progress.
C onnect to
Control signal for SW3
NOTES: 1. Use only as a standard for designing this data. Mass production may cause some changes in device characteristics.
Figure 16.8
Internal Equivalent Circuit of Analog Input
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16. A/D Converter
16.6
Inflow Current Bypass Circuit
Figure 16.9 shows the Configuration of the Inflow Current Bypass Circuit, Figure 16.10 shows the Example of an Inflow Current Bypass Circuit where VCC or More is Applied.
OFF Unselected Channel Fixed to GND level ON
OFF
To the internal logic of the A/D Converter ON Selected Channel External input latched into OFF ON
Figure 16.9
Configuration of the Inflow Current Bypass Circuit
VCC or more Leakage Current Generated Unselected Channel OFF Leakage Current Generated ON OFF
Unaffected by leakage
To the internal logic of the A/D Converter
Sensor Input
Selected Channel
ON
ON
OFF
Figure 16.10
Example of an Inflow Current Bypass Circuit where VCC or More is Applied
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17. Programmable I/O Ports
17. Programmable I/O Ports
Programmable Input/Output ports (hereafter referred to as "I/O ports") have 13 ports of the P1, P3_3 to P3_5, P3_7, and P4_5. Also, the main clock oscillation circuit is not used, the P4_6 and P4_7 can be used as the input port only. Table 17.1 lists the Overview of Programmable I/O Ports.
Table 17.1 Overview of Programmable I/O Ports
Ports P1 P3_3, P4_5 P4_6, P4_7(3)
I/O I/O I/O I
Output Form CMOS3 State CMOS3 State CMOS3 State (Without output function)
I/O Setting
Internal Pull-Up Resistor
Drive Capacity Selection
Set every bit Set every 4 bits(1) Set every bit(2) of P1_0 to P1_3 (1) Set every bit Set every bit None Set every bit Set every 3 bits(1) None None None None
P3_4, P3_5, P3_7 I/O
NOTES: 1. In input mode, whether the internal pull-up resistor is connected or not can be selected by the PUR0 and PUR1 registers. 2. This port can be used as the LED drive port by setting the DRR register to "1" (High). 3. When the main clock oscillation circuit is not used, these ports can be used as the input port only.
17.1
Functions of Programmable I/O Ports
The PDi_j (j=0 to 7) bit in the PDi (i=1,3 and 4) register controls I/O of the ports P1, P3_3 to P3_5, P3_7 and P4_5. The Pi register consists of a port latch to hold output data and a circuit to read pin state. Figures 17.1 to 17.3 show the Configurations of Programmable I/O Ports. Table 17.2 lists the Functions of Programmable I/O Ports. Also, Figure 17.5 shows the PD1, PD3 and PD4 Registers. Figure 17.6 shows the P1, P3 and P4 Registers, Figure 17.7 shows the PUR0 and PUR1 Registers and Figure 17.8 shows the DRR Register.
Table 17.2 Functions of Programmable I/O Ports
Operation When Value of PDi_j Bit in PDi Register(1) Accessing When PDi_j bit is set to "0" (input mode) When PDi_j bit is set to "1" (output mode) Pi Register Reading Read pin input level Read the port latch Writing Write to the port latch Write to the port latch. The value written in the port latch, it is output from the pin. NOTES: 1. Nothing is assigned to the PD3_0 to PD3_2, PD3_6, PD4_0 to PD4_4, PD4_6 and PD4_7 bits.
17.2
Effect on Peripheral Functions
Programmable I/O ports function as I/O of peripheral functions (Refer to Table 1.6 Pin Name Information by Pin Number). Table 17.3 lists the Setting of PDi_j Bit When Functioning as I/O of Peripheral Functions. Refer to descriptions of each function for how to set peripheral functions.
Table 17.3 Setting of PDi_j Bit When Functioning as I/O of Peripheral Functions
I/O of Peripheral Functions PDi_j Bit Setting of Port shared with Pin Input Set this bit to "0" (input mode). Output This bit can be set to both "0" and "1" (output regardless of the port setting)
17.3
Pins Other than Programmable I/O Ports
Figure 17.4 shows the Configuration of I/O Pins.
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17. Programmable I/O Ports
P1_0 to P1_3
Direction Register
Pull-up Selection
"1" Output from each peripheral function Data Bus Port Latch (Note 1)
Drive Capacity Selection Input to each peripheral function Analog Input
P1_4
Direction Register
Pull-Up Selection
"1"
Output from each peripheral function Data Bus Port Latch (Note 1)
P1_5
Direction Register
Pull-Up Selection
Data Bus
Port Latch (Note 1)
Input to each peripheral function
NOTES : 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC.
Figure 17.1
Configuration of Programmable I/O Ports (1)
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17. Programmable I/O Ports
P1_6, P1_7
Direction Register
Pull-Up Selection
"1" Output from each peripheral function Data Bus Port Latch (Note 1)
Input to each peripheral function
P3_3
Direction Register
Pull-Up Selection
"1"
Output from each peripheral function Data Bus Port Latch (Note 1)
Input to each peripheral function
Digital Filter
P3_4, P3_5, P3_7
Direction Register
Pull-Up Selection
"1" Output from each peripheral function Data Bus Port Latch (Note 1)
Input to each peripheral function NOTES : 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC.
Figure 17.2
Configuration of Programmable I/O Ports (2)
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P4_5
Direction Register
Pull-Up Selection
Data Bus
Port Latch (Note 4)
Input to each peripheral function
Digital Filter
P4_6/XIN
Data Bus (Note 4) Clocked Inverter(1)
(Note 2)
P4_7/XOUT
(Note 3) Data Bus (Note 4)
NOTES: 1. When CM05=1, CM10=1, or CM13=0, the clocked inverter is cutoff. 2. When CM10=1 or CM13=0, the feedback resistor is unconnected. 3. When CM05=CM13=1 or CM10=CM13=1, this pin is pulled up. 4. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC.
Figure 17.3
Configuration of Programmable I/O Ports (3)
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17. Programmable I/O Ports
MODE
MODE Signal Input
(Note 1)
RESET
RESET Signal Input
(Note 1) NOTES : 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC.
Figure 17.4
Configuration of I/O Pins
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17. Programmable I/O Ports
Port Pi Direction Register (i=1, 3, 4)(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD1 PD3 PD4 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Address 00E3h 00E7h 00EAh Bit Name Port Pi0 Direction Bit Port Pi1 Direction Bit Port Pi2 Direction Bit Port Pi3 Direction Bit Port Pi4 Direction Bit Port Pi5 Direction Bit Port Pi6 Direction Bit Port Pi7 Direction Bit
After Reset 00h 00h 00h Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
RW RW RW RW RW RW RW RW RW
NOTES : 1. Bits PD3_0 to PD3_2 and PD3_6 in the PD3 register are unavailable on this MCU. If it is necessary to set bits PD3_0 to PD3_2 and PD3_6, set to "0" (input mode). When read, the content is "0". 2. Bits PD4_0 to PD4_4, PD4_6 and PD4_7 in the PD4 register are unavailable on this MCU. If it is necessary to set bits PD4_0 to PD4_4, PD4_6 and PD4_7, set to "0" (input mode). When read, the content is "0".
Figure 17.5
PD1, PD3 and PD4 Registers
Port Pi Register (i=1, 3, 4)(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P1 P3 P4 Bit Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Address 00E1h 00E5h 00E8h Bit Name Port Pi0 Bit Port Pi1 Bit Port Pi2 Bit Port Pi3 Bit Port Pi4 Bit Port Pi5 Bit Port Pi6 Bit Port Pi7 Bit
After Reset Indeterminate Indeterminate Indeterminate Function The pin level on any I/O port w hich is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port w hich is set for output mode can be controlled by w riting to the corresponding bit in this register. 0 : "L" level 1 : "H" level(1)
RW RW RW RW RW RW RW RW RW
NOTES : 1. Bits P3_0 to P3_2 and P3_6 in the P3 register are unavailable on this MCU. If it is necessary to set bits P3_0 to P3_2 and P3_6, set to "0" ("L" level). When read, the content is "0". 2. Bits P4_0 to P4_4 in the P4 register are unavailable on this MCU. If it is necessary to set bits P4_0 to P4_4, set to "0" ("L" level). When read, the content is "0".
Figure 17.6
P1, P3 and P4 Registers
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Pull-Up Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol PUR0 Bit Symbol (b1-b0) PU02 PU03 -- (b5-b4) PU06 PU07
A ddress 00FCh Bit Name
A f ter Reset 00XX0000b Function
Set to "0" Reserved Bit 0 : Not pulled up P1_0 to P1_3 pull-up(1) 1 : Pulled up P1_4 to P1_7 pull-up(1) Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate. P3_3 pull-up P3_4 to P3_5 and P3_7 pll-up(1)
(1)
RW RW RW RW -- RW RW
0 : Not pulled up 1 : Pulled up
NOTES : 1. When this bit is set to "1" (pulled up), the pin w hose direct bit is set to "0" (input mode) is pulled up.
Pull-up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 00FDh PUR1 Bit Symbol Bit Name -- Nothing is assigned. When w rite, set to "0". (b0) When read, its content is indeterminate. PU11 -- (b7-b2) P4_5 pull-up(1)
After Reset XXXXXX0Xb Function
RW -- RW --
0 : Not pulled up 1 : Pulled up
Nothing is assigned. When w rite, set to "0". When read, its content is indeterminate.
NOTES : 1. When the PU11 bit is set to "1" (pulled up) and the PD4_5 bit is set to "0" (input mode), the P4_5 pin is pulled up.
Figure 17.7
PUR0 and PUR1 Registers
Port P1 Drive Capacity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol DRR Bit Symbol DRR0 DRR1 DRR2 DRR3 (b7-b4)
Address 00FEh Bit Name P1_0 Drive Capacity P1_1 Drive Capacity P1_2 Drive Capacity P1_3 Drive Capacity Reserved Bit
After Reset 00h Function Set P1 N-channel output transistor drive capacity 0 : Low 1 : High Set to "0"
RW RW RW RW RW RW
Figure 17.8
DRR Register
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17.4
Port setting
Table 17.4 to Table 17.17 list the port setting. Table 17.4
Register Bit
Port P1_0/KI0/AN8/CMP0_0 Setting
PD1 PD1_0 0 0 0 PUR0 PU02 0 1 0 0 X X X DRR DRR0 X X X X 0 1 X KIEN KI0EN X X 1 X X X X ADCON0 CH2, CH1, CH0, ADGSEL0 XXXXb XXXXb XXXXb 1001b XXXXb XXXXb XXXXb TCOUT TCOUT0 0 0 0 0 0 0 1 Function Input port (not pulled up) Input port (pulled up) KI0 input A/D Converter input (AN8) Output port Output port (High drive) CMP0_0 output
Setting Value
0 1 1 X
X: "0" or "1"
Table 17.5
Register Bit
Port P1_1/KI1/AN9/CMP0_1 Setting
PD1 PD1_1 0 0 0 PUR0 PU02 0 1 0 0 X X X DRR DRR1 X X X X 0 1 X KIEN KI1EN X X 1 X X X X ADCON0 CH2, CH1, CH0, ADGSEL0 XXXXb XXXXb XXXXb 1011b XXXXb XXXXb XXXXb TCOUT TCOUT1 0 0 0 0 0 0 1 Function Input port (not pulled up) Input port (pulled up) KI1 input A/D Converter input (AN9) Output port Output port (High drive) CMP0_1 output
Setting Value
0 1 1 X
X: "0" or "1"
Table 17.6
Register Bit
Port P1_2/KI2/AN10/CMP0_2 Setting
PD1 PD1_2 0 0 0 PUR0 PU02 0 1 0 0 X X X DRR DRR2 X X X X 0 1 X KIEN KI2EN X X 1 X X X X ADCON0 CH2, CH1, CH0, ADGSEL0 XXXXb XXXXb XXXXb 1101b XXXXb XXXXb XXXXb TCOUT TCOUT2 0 0 0 0 0 0 1 Function Input port (not pulled up) Input port (pulled up) KI2 input A/D Converter input (AN10) Output port Output port (High drive) CMP0_2 input
Setting Value
0 1 1 X
X: "0" or "1"
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Table 17.7
Register Bit
Port P1_3/KI3/AN11/TZOUT Setting
PD1 PD1_3 0 0 0 0 PUR0 PU02 0 1 0 0 X X X X X X DRR DRR3 X X X X 0 1 0 1 X X KIEN KI3EN X X 1 X X X X X X X ADCON0 CH2, CH1, CH0, ADGSEL0 XXXXb XXXXb XXXXb 1111b XXXXb XXXXb XXXXb XXXXb XXXXb XXXXb TZMR TZMOD1, TZMOD0 00b 00b 00b 00b 00b 00b 01b 01b 01b 1Xb TZOC TZOCNT X X X X X X 1 1 0 X Function Input port (not pulled up) Input port (pulled up) KI3 input A/D Converter input (AN11) Output port Output port (High drive) Output port Output port (High drive) TZOUT output TZOUT output
Setting Value
1 1 X X X X
X: "0" or "1"
Table 17.8
Register Bit
Port P1_4/TXD0 Setting
PD1 PD1_4 0 0 1 PUR0 PU03 0 1 X U0MR SMD2, SMD1, SMD0 000b 000b 000b 001b U0C0 NCH X X X Function Input port (not pulled up) Input port (pulled up) Output port
Setting Value
X
X
100b 101b 110b 001b
0
TXD0 output, CMOS output
X
X
100b 101b 110b
1
TXD0 output, N-channel open output
X: "0" or "1"
Table 17.9
Register Bit
Port P1_5/RXD0/CNTR01/INT11 Setting
PD1 PD1_5 0 0 PUR0 PU03 0 1 X X X X UCON CNTRSEL X X X 1 X 1 TXMR TXMOD1, TXMOD0 XXb XXb Other than 01b Other than 01b Other than 01b Other than 01b Function Input port (not pulled up) Input port (pulled up) RXD0 input CNTR01/INT11 input Output port CNTR01 output
Setting Value
0 0 1 1
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17. Programmable I/O Ports
Table 17.10
Register Bit
Port P1_6/CLK0/SSI Setting
PD1 PD1_6 0 0 PUR0 PU03 0 1 0 X X U0MR SMD2, SMD1, SMD0, CKDIR Other than 0X10b Other than 0X10b XXX1b Other than 0X10b 0X10b Function Input port (not pulled up) Input port (pulled up) CLK0 (external clock) input Output port CLK0 (internal clock) output
Setting Value
0 1 X
X: "0" or "1"
Table 17.11
Register Bit
Port P1_7/CNTR00/INT10 Setting
PD1 PD1_7 0 0 PUR0 PU03 0 1 0 X X TXMR TXMOD1, TXMOD0 Other than 01b Other than 01b Other than 01b Other than 01b Other than 01b UCON CNTRSEL X X 0 X 0 Function Input port (not pulled up) Input port (pulled up) CNTR00/INT10 input Output port CNTR00 output
Setting Value
0 1 X
X: "0" or "1"
Table 17.12
Register Bit
Port P3_3/TCIN/INT3/SSI/CMP1_0 Setting
PD3 PD3_3 0 0 X PUR0 PU06 0 1 0 X X X X SSU (Refer to Table 15.3 Association between Communication Modes and I/O Pins) SSI Output Control 0 0 0 0 0 1 1 SSI Input Control 0 0 1 0 0 0 1 TCOUT TCOUT3 0 0 X 0 1 X 0 Input port (not pulled up) Input port (pulled up) SSI input Output port CMP1_0 output SSI output TCIN input/INT3
Function
Setting Value
1 X X 0
X: "0" or "1"
Table 17.13
Register Bit
Port P3_4/SCS/CMP1_1 Setting
PD3 PD3_4 0 0 PUR0 PU07 0 1 0 X X X SSU (Refer to Table 15.3 Association between Communication Modes and I/O Pins) SCS Output Control 0 0 0 0 0 1 SCS Input Control 0 0 1 0 0 0 TCOUT TCOUT4 0 0 0 0 1 X Input port (not pulled up) Input port (pulled up) SCS input Output port CMP1_1 output SCS output
Function
Setting Value
0 1 X X
X: "0" or "1"
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Table 17.14
Register Bit
Port P3_5/SSCK/CMP1_2 Setting
PD3 PD3_5 0 0 PUR0 PU07 0 1 0 X X X SSU (Refer to Table 15.3 Association between Communication Modes and I/O Pins) SSCK Output Control 0 0 0 0 0 1 SSCK Input Control 0 0 1 0 0 0 TCOUT TCOUT5 0 0 0 0 1 X Input port (not pulled up) Input port (pulled up) SSCK input Output port CMP1_2 output SSCK output
Function
Setting Value
0 1 X X
X: "0" or "1"
Table 17.15
Register
Port P3_7/CNTR0/SSO Setting
PD3 PUR0 SSU (Refer to Table 15.3 Association between Communication Modes and I/O Pins) SSO Output Control 0 0 0 0 0 1 SSO Input Control 0 0 0 0 1 0 TXMR UCON Function TXOCNT 0 0 0 1 X X U1SEL1, U1SEL0 0Xb 0Xb 0Xb XXb XXb XXb Input port (not pulled up) Input port (pulled up) Output port CNTR0 output pin SSO input pin SSO output pin
Bit
PD3_7 0 0
PU07 0 1 X X X X
Setting Value
1 X X X
X: "0" or "1"
Table 17.16
Register Bit
Port XIN/P4_6, XOUT/P4_7 Setting
CM1 CM13 1 1 CM1 CM10 1 0 0 0 X CM0 CM05 1 1 1 0 X Circuit Specification Oscillation Buffer OFF OFF OFF ON OFF Feedback Resistance OFF ON ON ON OFF Function XIN-XOUT oscillation stop External input to XIN pin, "H" output from XOUT pin XIN-XOUT oscillation stop XIN-XOUT oscillation Input port
Setting Value
1 1 0
X: "0" or "1"
Table 17.17
Register Bit
Port P4_5/INT0 Setting
PD4 PD4_5 0 PUR1 PU11 0 1 0 X INTEN INT0EN 0 0 1 X Function Input port (not pulled up) Input port (pulled up) INT0 input Output port
Setting Value
0 0 1
X: "0" or "1"
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17.5
Unassigned Pin Handling
Table 17.18 lists the Unassigned Pin Handling. Figure 17.9 show the Unassigned Pin Handling.
Table 17.18 Unassigned Pin Handling
Pin Name Ports P1, P3_3 to P3_5, P3_7, P4_5 Ports P4_6, P4_7 AVCC, VREF RESET (3)
Connection * After setting to input mode, connect every pin to VSS via a resistor (pulldown) or connect every pin to VCC via a resistor (pull-up).(2) * After setting to output mode, leave these pins open.(1, 2) Connect to VCC via a resistor (pull-up)(2) Connect to VCC Connect to VCC via a resistor (pull-up)(2)
NOTES: 1. When setting these ports to output mode and leaving them open, they remain input mode until they are switched to output mode by a program. The voltage level of these pins may be indeterminate and the power current may increase while the ports remain input mode. The content of the direction registers may change due to noise or out of control caused by noise. In order to enhance program reliability, set the direction registers periodically by a program. 2. Connect these unassigned pins to the microcomputer using the shortest wire length (within 2 cm) as possible. 3. When power-on reset function is used.
Microcomputer
Port P1, P3_3 to P3_5, (Input mode) P3_7, P4_5 : : (Input mode) (Output mode)
: : Open
Port P4_6, P4_7 RESET(1)
AVCC/VREF
NOTES: 1. When power-on reset function is used.
Figure 17.9
Unassigned Pin Handling
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18. Flash Memory Version
18. Flash Memory Version
18.1 Overview
In the flash memory version, rewrite operations to the flash memory can be performed in three modes; CPU rewrite, standard serial I/O, parallel I/O modes. Table 18.1 lists the Flash Memory Version Performance (see Table 1.1 Performance Outline of the R8C/ 14 Group and Table 1.2 Performance Outline of the R8C/15 Group for the items not listed on Table 18.1).
Table 18.1 Flash Memory Version Performance
Item Flash Memory Operating Mode Division of Erase Block Program Method Erase Method Program, Erase Control Method Rewrite Control Method
Number of Commands Block0 and 1 Program and (Program ROM) Erase (1) BlockA and B 10,000 times Endurance (2) (Data flash) ID Code Check Function Standard serial I/O mode supported ROM Code Protect For parallel I/O mode supported
Specification 3 modes (CPU rewrite, standard serial I/O, and parallel I/O mode) See Figure 18.1 and Figure 18.2 Byte unit Block erase Program and erase control by software command Rewrite control for Block 0 and 1 by FMR02 bit in FMR0 register Rewrite control for Block 0 by FMR16 bit and Block 1 by FMR16 bit 5 commands R8C/14 Group : 100 times ; R8C/15 Group : 1,000 times
NOTES: 1. Definition of program and erase endurance. The program and erase endurance is defined to be per-block. When the program and erase endurance is n times (n=100 or 10,000 times), to erase n times per block is possible. For example, if performing one-byte write to the distinct addresses on Block A of 1K-byte block 1,024 times and then erasing that block, the program and erase endurance is counted as one time. If rewriting more than 100 times, execute the program until the blank areas are all used to reduce the substantial rewrite endurance and then erase. Do not rewrite only particular blocks and rewrite to average the program and erase endurance to each block. Also keep the erase endurance as information and set up the limit endurance. 2. Blocks A and B are embedded only in the R8C/15 group.
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18. Flash Memory Version
Table 18.2
Flash Memory Rewrite Modes
Flash Memory Rewrite mode Function
CPU Rewrite Mode
Standard Serial I/O Mode User ROM area is rewritten by using a dedicated serial programmer.
Parallel I/O mode User ROM area is rewritten by using a dedicated parallel programmer.
User ROM area is rewritten by executing software commands from the CPU. EW0 mode: Rewritable in any area other than flash memory EW1 mode: Rewritable in flash memory Areas which can User ROM area be rewritten Operating Mode Single chip mode ROM None Programmer
User ROM area Boot mode Serial programmer
User ROM area Parallel I/O mode Parallel programmer
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18. Flash Memory Version
18.2
Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 18.1 shows the Flash Memory Block Diagram for R8C/14 Group. Figure 18.2 shows the Flash Memory Block Diagram for R8C/15 Group. The user ROM area of R8C/15 group contains an area (program ROM) which stores a microcomputer operating program and the 1-Kbyte Block A and B (data flash). The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite and standard serial I/O and parallel I/O modes. When rewriting the Block 0 and Block 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to "1" (rewrite enables), and when setting the FMR15 bit in the FMR1 register to "0" (rewrite enables), Block 0 is rewritable. When setting the FMR16 bit to "0" (rewrite enables), Block 1 is rewritable. The rewrite control program for standard serial I/O mode is stored in boot ROM area before shipment. The boot ROM area and the user ROM area share the same address, but have an another memory.
16 Kbytes ROM Product 0C000h Block 1 : 8 Kbytes(1) 12 Kbytes ROM Product 0D000h Block 1 : 4 Kbytes 0DFFFh 0E000h Block 0 : 8 Kbytes(1) 0DFFFh 0E000h Block 0 : 8 Kbytes(1)
(1)
Program ROM 8 Kbytes ROM Product 0E000h Block 0 : 8 Kbytes(1) 0E000h 8 Kbytes
0FFFFh User ROM Area
0FFFFh User ROM Area
0FFFFh User ROM Area
0FFFFh Boot ROM Area (Reserved Area)(2)
NOTES: 1. When setting the FMR02 bit in the FMR0 register to "1" (enables to rewrite) and the FMR15 bit in the FMR1 register to "0" (enable to rewrite), Block 0 is rewritable. When setting the FMR16 bit to "0" (enables to rewrite), Block 1 is rewritable (only for CPU rewrite mode). 2. This area is to store the boot program provided by Renesas Technology.
Figure 18.1
Flash Memory Block Diagram for R8C/14 Group
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18. Flash Memory Version
16 Kbytes ROM Product 02400h Block A : 1 Kbyte Block B : 1 Kbyte 02400h
12 Kbytes ROM Product Block A : 1 Kbyte Block B : 1 Kbyte 02400h
8 Kbytes ROM Product Block A : 1 Kbyte Data flash Block B : 1 Kbyte
02BFFh
02BFFh
02BFFh
0C000h Program ROM Block 1 : 8 Kbytes(1) 0D000h Block 1 : 4 Kbytes(1) 0DFFFh 0E000h Block 0 : 8 Kbytes(1) 0FFFFh User ROM Area 0FFFFh User ROM Area 0DFFFh 0E000h Block 0 : 8 Kbytes(1) 0E000h Block 0 : 8 Kbytes(1) 0E000h 8 Kbytes 0FFFFh User ROM Area Boot ROM Area (Reserved Area)(2)
0FFFFh
NOTES: 1. When setting the FMR02 bit in the FMR0 register to "1" (enables to rewrite) and the FMR15 bit in the FMR1 register to "0" (enables to rewrite), Block 0 is rewritable. When setting the FMR16 bit to "0" (enables to rewrite), Block 1 is rewritable (only for CPU rewrite mode). 2. This area is to store the boot program provided by Renesas Technology.
Figure 18.2
Flash Memory Block Diagram for R8C/15 Group
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18. Flash Memory Version
18.3
Functions To Prevent Flash Memory from Rewriting
Standard serial I/O mode contains an ID code check function, and the parallel I/O mode contains a ROM code protect function to prevent the flash memory from reading or rewriting easily.
18.3.1
ID Code Check Function
Use this function in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are determined whether they match. If the ID codes do not match, the commands sent from the programmer are not acknowledged. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh, 00FFF3h, 00FFF7h, and 00FFFBh. Write a program in which the ID codes are set at these addresses and write it in the flash memory.
Address
00FFDFh to 00FFDCh 00FFE3h to 00FFE0h 00FFE7h to 00FFE4h 00FFEBh to 00FFE8h 00FFEFh to 00FFECh 00FFF3h to 00FFF0h 00FFF7h to 00FFF4h 00FFFBh to 00FFF8h 00FFFFh to 00FFFCh
ID1 ID2 ID3 ID4 ID5 ID6 ID7
Undefined Instruction Vector
Overflow Vector BRK Instruction Vector Address Match Vector Single Step Vector
Oscillation Stop Detection/Watchdog Timer/Voltage Monitor 2 Vector
Address Break (Reserved)
(Note 1) Reset Vector
4 bytes
NOTES: 1. The OFS register is assigned to 00FFFFh. Refer to Figure 12.2 OFS, WDC, WDTR and WDTS registers for the OFS register details.
Figure 18.3
Address for ID Code Stored
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18. Flash Memory Version
18.3.2
ROM Code Protect Function
The ROM code protect function disables to read and change the internal flash memory by the OFS register in parallel I/O mode. Figure 18.4 shows the OFS Register. The ROM code protect function is enabled by writing "0" to the ROMCP1 bit and "1" to the ROMCR bit and disables to read and change the internal flash memory. Once the ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or standard serial I/O mode.
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
111
1
Symbol OFS Bit Symbol WDTON -- (b1) ROMCR ROMCP1 -- (b6-b4)
Address 0FFFFh Bit Name Watchdog Timer Start Select Bit Reserved Bit ROM Code Protect Disabled Bit ROM Code Protect Bit Reserved Bit
Before Shipment FFh(2) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to "1" 0 : ROM code protect disabled 1 : ROMCP1enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to "1"
RW RW RW RW RW RW
0 : Count source protect mode after reset enabled Count Source Protect CSPROINI Mode After Reset Select 1 : Count source protect mode after reset disabled Bit NOTES : 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. 2. If the block including the OFS register is erased, "FFh" is set to the OFS register.
RW
Figure 18.4
OFS Register
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18. Flash Memory Version
18.4
CPU Rewrite Mode
In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on a board without using such as a ROM programmer. Execute the program and block erase commands only to each block in user ROM area. When an interrupt request is generated during an erase operation in CPU rewrite mode, the flash module contains an erase-suspend function which performs the interrupt process after the erase operation is halted temporarily. During the erase-suspend, user ROM area can be read by a program. CPU rewrite mode contains erase write 0 mode(EW0 mode) and erase write 1 mode(EW1 mode). Table 18.3 lists the Differences between EW0 Mode and EW1 Mode.
Table 18.3 Differences between EW0 Mode and EW1 Mode
Item Operating Mode Area in which rewrite control program can be located Area in which rewrite control program can be executed Area which can be rewritten
EW0 Mode Single chip mode User ROM area
EW1 Mode Single chip mode User ROM area
Necessary to transfer to any areas other than the flash memory (e.g., RAM) before executing User ROM area
Executing directly on user ROM area is possible User ROM area However, other than the blocks which contain a rewrite control program(1) * Program, block erase command Disable to execute on any block which contains a rewrite control program * Disables to execute the read status register command Read array mode
Software Command Restriction
None
Mode after Program or Erase CPU Status during AutoWrite and Auto-Erase Flash Memory Status Detection
Read status register mode Operating
Condition for Transition to Erase-Suspend
CPU Clock
Hold state (I/O ports hold state before the command is executed) Read the FMR00, FMR06, and * Read the FMR00, FMR06, and FMR07 bits in the FMR0 register by FMR07 bits in the FMR0 register by a a program program * Execute the read status register command and read the SR7, SR5, and SR4 bits in the status register. The FMR40 bit in the FMR4 register Set the FMR40 and FMR41 bits in is set to "1" and the interrupt request the FMR4 register to "1" by a of the enabled maskable interrupt is program. generated 5MHz or below No restriction to the following (clock frequency to be used)
NOTES: 1. When setting the FMR02 bit in the FMR0 register to "1" (rewrite enables) and rewriting Block 0 is enabled by setting the FMR15 bit in the FMR1 register to "0" (rewrite enables). Rewriting Block 1 is enabled by setting the FMR16 bit to "0" (rewrite enables).
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18. Flash Memory Version
18.4.1
EW0 Mode
The microcomputer enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to "1" (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is set to "0", EW0 mode is selected. Use software commands to control a program and erase operations. The FMR0 register or the status register can determine status when program and erase operation complete. When entering an erase-suspend, set the FMR40 bit to "1" (enables erase-suspend) and the FMR41 bit to "1" (requests erase-suspend). Wait for td(SR-ES) and ensure that the FMR46 bit is set to "1" (enables reading) before accessing the user ROM area. The auto-erase operation restarts by setting the FMR41 bit to "0" (erase restarts).
18.4.2
EW1 Mode
The microcomputer enters EW1 mode by setting the FMR11 bit to "1" (EW1 mode) after setting the FMR01 bit to "1" (CPU rewrite mode enabled). The FMR0 register can determine status when program and erase operation complete. Do not execute the read status register command in EW1 mode. To enable the erase-suspend function, execute the block erase command after setting the FMR40 bit to "1" (enables erase-suspend). The interrupt to enter an erase-suspend should be in interrupt enabled status. After passing td(SR-ES) since the block erase command is executed, an interrupt request is acknowledged. When an interrupt request is generated, the FMR41 bit is automatically set to "1" (requests erasesuspend) and the auto-erase operation is halted. If the auto-erase operation does not complete (FMR00 bit is "0") when the interrupt process completes, the auto-erase operation restarts by setting the FMR41 bit to "0" (erase restarts)
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18. Flash Memory Version
Figure 18.5 shows the FMR0 Register. Figure 18.6 shows the FMR1 and FMR4 Registers.
18.4.2.1
FMR00 Bit
This bit indicates the operating status of the flash memory. The bit is "0" during programming, erasing, or erase-suspend mode; otherwise, the bit is "1".
18.4.2.2
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to "1" (CPU rewrite mode).
18.4.2.3
FMR02 Bit
The Block1 and Block0 do not accept the Program and Block Erase commands if the FMR02 bit is set to "0" (rewrite disabled). The Block0 and Block1 are controlled rewriting in the FMR15 and FMR16 bits if the FMR02 bit is set to "1" (rewrite enabled).
18.4.2.4
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. The flash memory is disabled against access by setting the FMSTP bit to "1". Therefore, the FMSTP bit must be written to by a program in other than the flash memory. In the following cases, set the FMSTP bit to "1": * When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to "1" (ready)) * When entering on-chip oscillator mode (main clock stop) Figure 18.10 shows a flow chart to be followed before and after entering on-chip oscillator mode (main clock stop). Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode.
18.4.2.5
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to "1" when a program error occurs; otherwise, it is cleared to "0". For details, refer to the description of the 18.4.5 Full Status Check.
18.4.2.6
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to "1" when an erase error occurs; otherwise, it is set to "0". Refer to 18.4.5 Full Status Check for the details.
18.4.2.7
FMR11 Bit
Setting this bit to "1" (EW1 mode) places the microcomputer in EW1 mode.
18.4.2.8
FMR15 Bit
When the FMR02 bit is set to "1" (rewrite enabled) and the FMR15 bit is set to "0" (rewrite enabled), the Block0 accepts the program command and block erase command.
18.4.2.9
FMR16 Bit
When the FMR02 bit is set to "1" (rewrite enabled) and the FMR16 bit is set to "0" (rewrite enabled), the Block1 accepts the program command and block erase command.
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18. Flash Memory Version
18.4.2.10 FMR40 bit
The erase-suspend function is enabled by setting the FMR40 bit to "1" (enable).
18.4.2.11 FMR41 bit
In EW0 mode, the microcomputer enters erase-suspend mode when setting the FMR41 bit to "1" by a program. The FMR41 bit is automatically set to "1" (requests erase-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the microcomputer enters erasesuspend mode. Set the FMR41 bit to "0" (erase restart) when the auto-erase operation restarts.
18.4.2.12 FMR46 bit
The FMR46 bit is set to "0" (disable reading) during auto-erase execution and set to "1" (enables reading) in erase-suspend mode. Do not access to the flash memory while this bit is set to "0".
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol FMR0 Bit Symbol FMR00 FMR01 FMR02
Address 01B7h
____
After Reset 00000001b Function 0 : Busy (During w riting or erasing) 1 : READY 0 : CPU rew rite mode disabled 1 : CPU rew rite mode enabled 0 : Disables rew rite 1 : Enables rew rite 0 : Enables flash memory operation 1 : Stops flash memory (Enters low -pow er consumption state and flash memory is reset) Set to "0" 0 : Completed successfully 1 : Terminated by error 0 : Completed successfully 1 : Terminated by error RW RO RW RW
Bit Name
RY/BY Status Flag CPU Rew rite Mode Select Bit(1) Block 0, 1 Rew rite Enable Bit(2, 6) Flash Memory Stop Bit(3, 5)
FMSTP
RW
-- (b5-b4) FMR06 FMR07
Reserved Bit Program Status Flag(4) Erase Status Flag(4)
RW RO RO
NOTES : 1. When setting this bit to "1", set to "1" immediately after setting it first to "0". Do not generate an interrupt betw een setting the bit to "0" and setting it to "1". Enter read array mode and set this bit to "0". 2. Set this bit to "1" immediately after setting this bit first to "0" w hile the FMR01 bit is set to "1". Do not generate an interrupt betw een setting the bit to "0" and setting it to "1". 3. Set this bit by a program in a space other than the flash memory. 4. This bit is set to "0" by executing the clear status command. 5. This bit is enabled w hen the FMR01 bit is set to "1" (CPU rew rite mode). When the FMR01 bit is set to "0" and w riting "1" to the FMSTP bit, the FMSTP bit is set to "1". The flash memory does not enter low -pow er consumption stat nor is reset. 6. When setting the FMR01 bit to "0" (CPU rew rite mode disabled), the FMR02 bit is set to "0" (disables rew rite).
Figure 18.5
FMR0 Register
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18. Flash Memory Version
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
000
Symbol Address 01B5h FMR1 Bit Symbol Bit Name -- Reserved Bit (b0) FMR11 -- (b4-b2) FMR15 FMR16 -- (b7) EW1 Mode Select Bit(1, 2) Reserved Bit Block 0 Rew rite Disable Bit(2,3) Block 1 Rew rite Disable Bit(2,3) Reserved Bit
After Reset 1000000Xb Function When read, its content is indeterminate. 0 : EW0 mode 1 : EW1 mode Set to "0" 0 : Enables rew rite 1 : Disables rew rite 0 : Enables rew rite 1 : Disables rew rite Set to "1"
RW RO RW RW RW RW RW
NOTES : 1. When setting this bit to "1", set to "1" immediately after setting it first to "0" w hile the FMR01 bit is set to "1" (CPU rew rite mode enable) . Do not generate an interrupt betw een setting the bit to "0" and setting it to "1". 2. This bit is set to "0" by setting the FMR01 bit to "0" (CPU rew rite mode disabled). 3. When the FMR01 bit is set to "1" (CPU rew rite mode enabled), the FMR15 and FMR16 bits can be w ritten. When setting this bit to "0", set to "0" immediately after setting it first to "1". When setting this bit to "1", set it to "1".
Flash Memory Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
0
0000
Symbol FMR4 Bit Symbol FMR40 FMR41 -- (b5-b2) FMR46 -- (b7)
Address 01B3h Bit Name Erase-Suspend Function Enable Bit(1) Erase-Suspend Request Bit(2) Reserved Bit Read Status Flag Reserved Bit
After Reset 01000000b Function 0 : Disable 1 : Enable 0 : Erase restart 1 : Erase-suspend request Set to "0" 0 : Disables reading 1 : Enables reading Set to "0"
RW RW RW RO RO RW
NOTES : 1. When setting this bit to "1", set to "1" immediately after setting it first to "0". Do not generate an interrupt betw een setting the bit to "0" and setting it to "1". 2. This bit is enabled w hen the FMR40 bit is set to "1" (enable) and this bit can be w ritten during the period betw een issuing an erase command and completing an erase (This bit is set to "0" during the periods other than above). In EW0 mode, this can be set to "0" and "1" by a program. In EW1 mode, this bit is automatically set to "1" if a maskable interrupt is generated during an erase operation w hile the FMR40 bit is set to "1". Do not set this bit to "1" by a program ("0" can be w ritten).
Figure 18.6
FMR1 and FMR4 Registers
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R8C/14 Group, R8C/15 Group Figure 18.7 shows the Timing on Suspend Operation.
18. Flash Memory Version
Erase Starts
Erase Suspends
Erase Restarts
Erase Ends
During Erase FMR00 Bit in FMR0 Register FMR46 Bit in FMR4 Register
"1" "0"
During Erase
"1" "0"
Check that the FMR00 bit is set to "0", and that the erase operation has not ended.
Check the Status, and that the erase operation ends normally.
Figure 18.7
Timing on Suspend Operation
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18. Flash Memory Version
Figure 18.8 shows the How to Set and Exit EW0 Mode. Figure 18.9 shows the How to Set and Exit EW1 Mode.
EW0 Mode Operating Procedure
Rewrite Control Program Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled)(2)
Set CM0 and CM1 registers(1) Execute software commands
Transfer a rewrite control program which uses CPU rewrite mode to any areas other than the flash memory
Execute the read array command(3)
Jump to the rewrite control program which has been transferred to any areas other than the flash memory (The subsequent process is executed by the rewrite control program in any areas other than the flash memory)
Write "0" to the FMR01 bit (CPU rewrite mode disabled)
Jump to a specified address in the flash memory
NOTES : 1. Select 5MHz or below for the CPU clock by the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. 2. When setting the FMR01 bit to "1", write "0" to the FMR01 bit before writing "1". Do not generate an interrupt between writing "0" and "1". 3. Disable the CPU rewrite mode after executing the read array command.
Figure 18.8
How to Set and Exit EW0 Mode
EW1 Mode Operating Procedure
Program in ROM
Write "0" to the FMR01 bit before writing "1" (CPU rewrite mode enabled)(1) Write "0" to the FMR11 bit before writing "1" (EW1 mode)
Execute Software Commands
Write "0" to the FMR01 bit (CPU rewrite mode disabled)
NOTES : 1. When setting the FMR01 bit to "1", write "0" to the FMR01 bit before writing "1". Do not generate an interrupt between writing "0" and "1".
Figure 18.9
How to Set and Exit EW1 Mode
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18. Flash Memory Version
On-Chip Oscillator Mode (Main Clock Stops) Program Transfer a on-chip oscillator mode (main clock stops) program to any areas other the flash memory Write "0" to the FMR01 bit before writing "1" (CPU rewrite mode enabled)
Jump to the on-chip oscillator mode (main clock stops) program which has been transferred to any areas other the flash memory. (The subsequent processing is executed by a program in any areas other than the flash memory.)
Write "1" to the FMSTP bit (Flash memory stops. Low power consumption state)(1)
Switch the clock source for the CPU clock. Turn XIN off
Process in on-chip oscillator mode (main clock stops)
Turn main clock onwait until oscillation stabilizesswitch the clock source for CPU clock(2)
Write "0" to the FMSTP bit (flash memory operation)(4)
Write "0" to the FMR01 bit (CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (15ms)(3)
Jump to a specified address in the flash memory
NOTES : 1. Set the FMR01 bit to "1" (CPU rewrite mode) before setting the FMSTP bit to "1" . 2. Before the clock source for CPU clock can be changed, the clock to which to be changed must be stable. 3. Insert a 15us wait time in a program. Do not access to the flash memory during this wait time. 4. Ensure 10us until setting "0" (flash memory operates) after setting the FMSTP bit to "1" (flash memory stops).
Figure 18.10
Process to Reduce Power Consumption in On-Chip Oscillator Mode (Main Clock Stops)
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18.4.3
Software Commands
Software commands are described below. Read or write commands and data from or to in 8-bit units.
Table 18.4 Software Commands
First Bus Cycle Command Read Array Read Status Register Clear Status Register Program Block Erase Mode Write Write Write Write Write Address x x x WA x Data Mode (D7 to D0) FFh 70h Read 50h 40h Write 20h Write
Second Bus Cycle Address Data (D7 to D0) SRD WD D0h
x WA BA
SRD: Status register data (D7 to D0)
WA: Write address (Ensure the address specified in the first bus cycle is the same address as the address specified in the second bus cycle.) WD: Write data (8 bits) BA: Given block address x: Any specified address in the user ROM area
18.4.3.1
Read Array Command
The read array command reads the flash memory. The microcomputer enters read array mode by writing "FFh" in the first bus cycle. If entering the read address after the following bus cycles, the content of the specified address can be read in 8-bit units. Since the microcomputer remains in read array mode until another command is written, the contents of multiple addresses can be read continuously.
18.4.3.2
Read Status Register Command
The read status register command reads the status register. If writing "70h" in the first bus cycle, the status register can be read in the second bus cycle. (Refer to 18.4.4 Status Register) When reading the status register, specify an address in the user ROM area. Do not execute this command in EW1 mode.
18.4.3.3
Clear Status Register Command
The clear status register command sets the status register to "0". If writing "50h" in the first bus cycle, the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be set to "0".
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18. Flash Memory Version
18.4.3.4
Program Command
The program command writes data to the flash memory in 1-byte units. Write "40h" in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register can determine whether auto programming has completed. The FMR00 bit is set to "0" during auto programming and set to "1" when auto programming completes. The FMR06 bit in the FMR0 register can determine the result of auto programming after it has been finished.(Refer to 18.4.5 Full Status Check) Do not write additions to the already programmed address. When the FMR02 bit in the FMR0 register is set to "0" (disable rewriting), or the FMR02 bit is set to "1" (rewrite enables) and the FMR15 bit in the FMR1 register is set to "1" (disable rewriting), the program command on Block 0 is not acknowledged. When the FMR16 bit is set to "1" (disable rewriting), the program command on Block 1 is not acknowledged. In EW1 mode, do not execute this command on any address at which the rewrite control program is allocated. In EW0 mode, the microcomputer enters read status register mode at the same time auto programming starts and the status register can be read. The status register bit 7 (SR7) is set to "0" at the same time auto programming starts and set back to "1" when auto programming completes. In this case, the microcomputer remains in read status register mode until a read array command is written next. Reading the status register can determine the result of auto programming after auto programming has completed.
Start
Write the command code `40h' to the write address
Write data to the write address
FMR00=1?
No
Yes Full status check
Program completed
Figure 18.11
Program Command
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18.4.3.5
Block Erase
If writing "20h" in the first bus cycle and "D0h" to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. The FMR00 bit in the FMR0 register can determine whether auto erasing has completed. The FMR00 bit is set to "0" during auto erasing and set to "1" when auto erasing completes. The FMR07 bit in the FMR0 register can determine the result of auto erasing after auto erasing has completed. (Refer to 18.4.5 Full Status Check) When the FMR02 bit in the FMR0 register is set to "0" (disable rewriting) or the FMR02 bit is set to "1" (rewrite enables) and the FMR15 bit in the FMR1 register is set to "1" (disable rewriting), the block erase command on Block 0 is not acknowledged. When the FMR16 bit is set to "1" (disable rewriting), the block erase command on Block 1 is not acknowledged. Figure 18.12 shows the Block Erase Command (When Not Using Erase-Suspend Function). Figure 18.13 shows the Block Erase Command (When Using Erase-Suspend Function). In EW1 mode, do not execute this command on any address at which the rewrite control program is allocated. In EW0 mode, the microcomputer enters read status register mode at the same time auto erasing starts and the status register can be read. The status register bit 7 (SR7) is set to "0" at the same time auto erasing starts and set back to "1" when auto erasing completes. In this case, the microcomputer remains in read status register mode until the read array command is written next.
Start
Write the command code `20h'
Write `D0h' to the given block address
FMR00=1?
No
Yes Full status check
Block erase completed
Figure 18.12
Block Erase Command (When Not Using Erase-Suspend Function)
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Start Maskable interrupt (1, 2)
FMR40=1
FMR41=1
Write the command code "20h"
FMR46=1 ? Yes
No
Write "D0h" to the any block address
Access to flash memory
FMR00=1? Yes Full status check
No
FMR41=0
REIT
Block erase completed
Maskable interrupt (2)
Start
FMR40=1
Access to flash memory
Write the command code "20h"
REIT
Write "D0h" to the any block address
FMR41=0
FMR00=1 ? Yes Full status check
No
Block erase completed
NOTES : 1. In EW0 mode, interrupt vector table and interrupt routine for an interrupt to be used should be allocated in RAM area. 2. td(SR-ES) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter an erase-suspend should be in interrupt enabled status.
Figure 18.13
Block Erase Command (When Using Erase-Suspend Function)
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18.4.4
Status Register
The status register indicates the operating status of the flash memory and whether an erasing or programming operation completes normally or in error. Status of the status register can be read by the FMR00, FMR06, and FMR07 bits in the FMR0 register. Table 18.5 lists the Status Register. In EW0 mode, the status register can be read in the following cases: * When a given address in the user ROM area is read after writing the read status register command * When a given address in the user ROM area is read after executing the program or block erase command but before executing the read array command.
18.4.4.1
Sequencer Status (SR7 and FMR00 Bits)
The sequencer status indicates operating status of the flash memory. SR7 = 0 (busy) during auto programming and auto erasing, and is set to "1" (ready) at the same time the operation completes.
18.4.4.2
Erase Status (SR5 and FMR07 Bits)
Refer to 18.4.5 Full Status Check.
18.4.4.3
Program Status (SR4 and FMR06 Bits)
Refer to 18.4.5 Full Status Check.
Table 18.5 Status Register
Status Register Bit SR0 (D0) SR1 (D1) SR2 (D2) SR3 (D3) SR4 (D4) SR5 (D5) SR6 (D6) SR7 (D7)
FMR0 Register Bit
- - - - FMR06
Status Name "0" Reserved Reserved Reserved Reserved Program status Erase status Reserved Sequencer status
- - - - Completed normally Completed normally - Busy
Contents "1"
- - - - Error - - - - 0
Value after Reset
FMR07
- FMR00
Error
- Ready
0
- 0
* D0 to D7: Indicates the data bus which is read when the read status register command is executed. * The FMR07 (SR5) to FMR06 bits (SR4) are set to "0" by executing the clear status register command. * When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to "1", the program and block erase command cannot be accepted.
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18. Flash Memory Version
18.4.5
Full Status Check
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to "1", indicating occurrence of each specific error. Therefore, Checking these status bits (full status check) can determine the executed result. Table 18.6 lists the Errors and FMR0 Register Status. Figure 18.14 shows the Full Status Check and Handling Procedure for Each Error.
Table 18.6 Errors and FMR0 Register Status
FRM00 Register (Status Register) Status Error FMR07(SR5) FMR06(SR4) 1 1 Command Sequence Error
Error occurrence condition * When any command is not written correctly * When invalid data other than those that can be written in the second bus cycle of the block erase command is written (i.e., other than "D0h" or "FFh")(1) * When executing the program command or block erase command while rewriting is disabled using the FMR02 bit in the FMR0 register, the FMR15 or FMR16 bit in the FMR1 register. * When inputting and erasing the address in which the Flash memory is not allocated during the erase command input * When executing to erase the block which disables rewriting during the erase command input. * When inputting and writing the address in which the Flash memory is not allocated during the write command input. * When executing to write the block which disables rewriting during the write command input. * When the block erase command is executed but not automatically erased correctly * When the program command is executed but not automatically programmed correctly.
1 0
0 1
Erase Error Program Error
NOTES: 1. The microcomputer enters read array mode by writing "FFh" in the second bus cycle of these commands, at the same time the command code written in the first bus cycle will disabled.
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Command sequence error
Full status check Execute the clear status register command (set these status flags to 0) FMR06 = 1 and FMR07 = 1? No Re-execute the command Yes
Command sequence error Check if command is properly input
FMR07 = 0? No
Yes
Erase error
Erase error
Execute the clear status register command (set these status flags to 0)
Erase command re-execution times 3 times? Yes Yes Re-execute block erase command
No
Block targeting for erasure cannot be used
FMR06 = 0? No
Program error
Program error
Execute the clear status register command (set these status flags to 0) Full status check completed Specify the other address besides the write address where the error occurs for the program address(1) NOTE: 1. To rewrite to the address where the program error occurs, check if the full status check is complete normally and write to the address after the block erase command is executed.
Re-execute program command
Figure 18.14
Full Status Check and Handling Procedure for Each Error
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18. Flash Memory Version
18.5
Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for this microcomputer. Standard serial I/O mode is used to connect with a serial writer using a special clock asynchronous serial I/O. There are three types of Standard serial I/O modes: * Standard serial I/O mode 1 .......... Clock synchronous serial I/O used to connect with a serial programmer * Standard serial I/O mode 2 .......... Clock asynchronous serial I/O used to connect with a serial programmer * Standard serial I/O mode 3 .......... Special clock asynchronous serial I/O used to connect with a serial programmer This microcomputer uses Standard serial I/O mode 2 and Standard serial I/O mode 3. Refer to Appendix 2. Connecting Example between Serial Writer and On-Chip Debugging Emulator. Contact the manufacturer of your serial programmer for serial programmer. Refer to the user's manual of your serial programmer for details on how to use it. Table 18.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 18.8 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3). Figure 18.15 show Pin Connections for Standard Serial I/O Mode 3. After processing the pins shown in Table 18.8 and rewriting a flash memory using a writer, apply "H" to the MODE pin and reset a hardware if a program is operated on the flash memory in single-chip mode.
18.5.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match (refer to 18.3 Functions To Prevent Flash Memory from Rewriting).
Table 18.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2)
Pin VCC,VSS RESET P4_6/XIN P4_7/XOUT AVCC, AVSS P1_0 to P1_7 VREF P3_3 to P3_5 MODE P3_7 P4_5
Name Power input Reset input P4_6 input/clock input P4_7 input/clock output Analog power supply input Input port P1 Reference voltage input Input port P3 MODE TXD output RXD input
I/O
I I I/O I I I I I/O O I
Description Apply the voltage guaranteed for program and erase to VCC pin and 0V to VSS pin. Reset input pin. Connect ceramic resonator or crystal oscillator between XIN and XOUT pins.
Connect AVSS to VSS and AVCC to VCC, respectively. Input "H" or "L" level signal or leave the pin open. Reference voltage input pin to A/D converter. Input "H" or "L" level signal or leave the pin open. Input "L". Serial data output pin. Serial data input pin.
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18. Flash Memory Version
Table 18.8
Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Pin VCC,VSS RESET P4_6/XIN P4_7/XOUT AVCC, AVSS VREF P1_0 to P1_7 P3_3 to P3_5, P3_7 P4_5 MODE
Name Power input Reset input P4_6 input/clock input P4_7 input/clock output Analog power supply input Reference voltage input Input port P1 Input port P3 Input port P4 MODE
I/O
I I
Description Apply the voltage guaranteed for program and erase to VCC pin and 0V to VSS pin. Reset input pin.
Connect ceramic resonator or crystal oscillator between XIN and XOUT pins when connecting external I/O oscillator. Apply "H" and "L" or leave the pin open when using as input port I I I I Connect AVSS to VSS and AVCC to VCC, respectively. Reference voltage input pin to A/D converter. Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open.
I Input "H" or "L" level signal or leave the pin open. I/O Serial data I/O pin. Connect to the flash programmer.
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18. Flash Memory Version
1 2 RESET Connect Oscillator Circuit(1) 3 4 VSS 5 6 7 MODE 8 9 10
20 19 18 17 16 15 14 13 12 11 VCC
Package: PLSP0020JB-A
NOTES: 1. No need to connect an oscillating circuit when operating with on-chip oscillator clock. Value
Voltage from programmer
R8C/14, R8C/15 Group
Mode Setting Signal MODE RESET
VSS VCC
Figure 18.15
Pin Connections for Standard Serial I/O Mode 3
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18. Flash Memory Version
18.5.1.1
Example of Circuit Application in the Standard Serial I/O Mode
Figure 18.16 show Pin Process in Standard Serial I/O Mode 2, Figure 18.17 show Pin Process in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer.
Microcomputer
Data Output
TXD
Data Input
RXD MODE
NOTES: 1. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the MODE input with a switch. 2. Connecting the oscillation is necessary. Set the main clock frequency 1 MHz to 20 MHz. Refer to Appendix 2.1 Connecting examples with M16C Flash Starter (M3A-0806).
Figure 18.16
Pin Process in Standard Serial I/O Mode 2
Microcomputer
MODE I/O MODE
Reset Input
RESET
User Reset Signal
NOTES: 1. Controlled pins and external circuits vary depending on the programmer. Refer to the programmer manual for details. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by connecting a programmer. 3. When operating with on-chip oscillator clock, connecting the oscillating circuit is not necessary.
Figure 18.17
Pin Process in Standard Serial I/O Mode 3
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18. Flash Memory Version
18.6
Parallel I/O Mode
Parallel I/O mode is used to input and output the required software command, address and data parallel to controls (read, program and erase) for internal flash memory. Use a parallel programmer which supports this microcomputer. Contact the manufacturer of your parallel programmer about the parallel programmer and refer to the user's manual of your parallel programmer for details on how to use it. User ROM area can be rewritten shown in Figures 18.1 and 18.2 in parallel I/O mode.
18.6.1
ROM Code Protect Function
The ROM code protect function disables to read and rewrite the flash memory. (Refer to the 18.3 Functions To Prevent Flash Memory from Rewriting.)
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19. Electrical Characteristics
19. Electrical Characteristics
Table 19.1
Symbol VCC AVCC VI VO Pd Topr Tstg
Absolute Maximum Ratings
Parameter Supply Voltage Analog Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Ambient Temperature Storage Temperature Condition VCC = AVCC VCC = AVCC Rated value -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 300 -20 to 85 / -40 to 85 (D version) -65 to 150 Unit V V V V mW C C
Topr = 25C
Table 19.2
Symbol VCC AVCC VSS AVSS VIH VIL IOH(sum)
Recommended Operating Conditions
Parameter Supply Voltage Analog Supply Voltage Supply Voltage Analog Supply Voltage Input "H" Voltage Input "L" Voltage Peak Sum Sum of All Output "H" Pins IOH (peak) Current Peak Output "H" Current Average Output "H" Current Peak Sum Sum of All Output "L" Pins IOL (peak) Currents Peak Output "L" Except P1_0 to P1_3 Currents P1_0 to P1_3 Drive Capacity HIGH Drive Capacity LOW Average Output Except P1_0 to P1_3 "L" Current P1_0 to P1_3 Drive Capacity HIGH Drive Capacity LOW Main Clock Input Oscillation Frequency 3.0V VCC 5.5V 2.7V VCC < 3.0V Conditions Min. 2.7 -
- -
Standard Typ. - VCC(3) 0 0 - - -
Max. 5.5 -
- -
Unit V V V V V V mA
0.8VCC 0 -
VCC 0.2VCC -60
IOH(peak) IOH(avg) IOL(sum)
- - -
- - -
-10 -5 60
mA mA mA
IOL(peak)
- - - - - -
- - - - - - - -
IOL(avg)
f(XIN)
0 0
10 30 10 5 15 5 20 10
mA mA mA mA mA mA MHz MHz
NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. The typical values when average output current is 100ms. 3. Hold VCC = AVCC.
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19. Electrical Characteristics
Table 19.3
Symbol
- -
A/D Converter Characteristics
Parameter Resolution Absolute Accuracy Conditions Vref = VCC AD = 10MHz, Vref = VCC = 5.0V AD = 10MHz, Vref = VCC = 5.0V
AD = 10MHz, Vref = VCC = 3.3V(3) AD = 10MHz, Vref = VCC = 3.3V(3) Vref = VCC AD = 10MHz, Vref = VCC = 5.0V AD = 10MHz, Vref = VCC = 5.0V
10-Bit Mode 8-Bit Mode 10-Bit Mode 8-Bit Mode
Min. - - - -
-
Standard Typ. Max. - 10 - 3 - 2 - 5
- - - -
Unit Bits LSB LSB LSB LSB k s
s
2 40 -
- -
Rladder tconv Vref VIA -
Resistor Ladder Conversion Time 10-Bit Mode 8-Bit Mode Reference voltage Analog Input Voltage A/D Operating Without Sample & Hold Clock With Sample & Hold Frequency(2)
10 3.3 2.8
-
VCC(4)
- - -
V V MHz MHz
0 0.25 1
Vref 10 10
NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. If f1 exceeds 10MHz, divide the f1 and hold A/D operating clock frequency (AD) 10MHz or below. 3. If the AVcc is less than 4.2V, divide the f1 and hold A/D operating clock frequency (AD) f1/2 or below. 4. Hold VCC = Vref
P1 P3 P4 30pF
Figure 19.1
Port P1, P3 and P4 Measurement Circuit
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19. Electrical Characteristics
Table 19.4
Symbol
- - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/Erase Endurance(2) Byte Program Time Block Erase Time Time Delay from Suspend Request until Erase Suspend Erase Suspend Request Interval Program, Erase Voltage Read Voltage Program, Erase Temperature Data Hold Time(7) Conditions R8C/14 Group R8C/15 Group VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C Min. 100(3) 1,000(3) - - - 10 2.7 2.7 0 20 Standard Typ. -
-
Max. -
-
Unit times times
s
td(SR-ES)
- - - - -
50 0.4 -
- - - - -
400 9 8
- 5.5 5.5 60 -
s ms ms V V C year
Ambient temperature = 55 C
NOTES: 1. VCC = AVcc = 2.7 to 5.5V at Topr = 0 to 60 C, unless otherwise specified. 2. Definition of program and erase The program and erase endurance shows an erase endurance for every block. If the program and erase endurance is "n" times (n = 100, 10000), "n" times erase can be performed for every block. For example, if performing 1-byte write to the distinct addresses on Block A of 1Kbyte block 1,024 times and then erasing that block, program and erase endurance is counted as one time. However, do not perform multiple programs to the same address for one time ease.(disable overwriting). 3. Endurace to guarantee all electrical characteristics after program and erase.(1 to "Min." value can be guaranateed). 4. In the case of a system to execute multiple programs, perform one erase after programming as reducing effective reprogram endurance not to leave blank area as possible such as programming write addresses in turn . If programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective reprogram endurance. Additionally, averaging erase endurance for Block A and B can reduce effective reprogram endurance more. To leave erase endurance for every block as information and determine the restricted endurance are recommended. 5. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 6. Customers desiring Program/Erase failure rate information should contact their Renesas technical support representative. 7. The data hold time incudes time that the power supply is off or the clock is not supplied.
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19. Electrical Characteristics
Table 19.5
Symbol
- - - - -
Flash Memory (Data flash Block A, Block B) Electrical Characteristics
Parameter Program/Erase Endurance(2) Byte Program Time (Program/Erase Endurance 1,000 Times) Byte Program Time (Program/Erase Endurance > 1,000 Times) Block Erase Time (Program/Erase Endurance 1,000 Times) Block Erase Time (Program/Erase Endurance > 1,000 Times) Time Delay from Suspend Request until Erase Suspend Erase Suspend Request Interval Program, Erase Voltage Read Voltage Program, Erase Temperature Data Hold Time(9) Conditions Standard Typ. - 10,000(3) Min.
- - - - -
Max. - 400
-
Unit times
s s
VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C
50 65 0.2 0.3
- - - - - -
9
-
s s ms ms V V C year
td(SR-ES)
- - - - -
8
- 5.5 5.5 85 -
10 2.7 2.7 -20(8) Ambient temperature = 55 C 20
NOTES: 1. VCC = AVcc = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. Definition of program and erase The program and erase endurance shows an erase endurance for every block. If the program and erase endurance is "n" times (n = 100, 10000), "n" times erase can be performed for every block. For example, if performing 1-byte write to the distinct addresses on Block A of 1Kbyte block 1,024 times and then erasing that block, program and erase endurance is counted as one time. However, do not perform multiple programs to the same address for one time ease.(disable overwriting). 3. Endurace to guarantee all electrical characteristics after program and erase.(1 to "Min." value can be guaranateed). 4. Standard of Block A and Block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times aer the same as that in program area. 5. In the case of a system to execute multiple programs, perform one erase after programming as reducing effective reprogram endurance not to leave blank area as possible such as programming write addresses in turn . If programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective reprogram endurance. Additionally, averaging erase endurance for Block A and B can reduce effective reprogram endurance more. To leave erase endurance for every block as information and determine the restricted endurance are recommended. 6. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 7. Customers desiring Program/Erase failure rate information should contact their Renesas technical support representative. 8. -40 C for D version. 9. The data hold time incudes time that the power supply is off or the clock is not supplied.
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19. Electrical Characteristics
Erase-Suspend Request (Maskable interrupt Request)
FMR46 td(SR-ES)
Figure 19.2
Time delay from Suspend Request until Erase Suspend
Table 19.6
Symbol Vdet1
- td(E-A)
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage Detection Level(3) Voltage Detection Circuit Self Power Consumption Waiting Time until Voltage Detection Circuit Operation Starts(2) Microcomputer Operating Voltage Minimum Value Condition Min. 2.70
- -
Standard Typ. Max. 2.85 3.00 600 -
- - 100 -
Unit V nA s V
VCA26 = 1, VCC = 5.0V
Vccmin
2.7
NOTES: 1. The measurement condition is VCC = AVCC = 2.7V to 5.5V and Topr = -40C to 85 C. 2. Necessary time until the voltage detection circuit operates when setting to "1" again after setting the VCA26 bit in the VCA2 register to "0". 3. Hold Vdet2 > Vdet1.
Table 19.7
Symbol Vdet2
- -
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage Detection Level(4) Voltage Monitor 2 Interrupt Request Generation Voltage Detection Circuit Self Power Consumption Waiting Time until Voltage Detection Circuit Operation Starts(3) Time(2) VCA27 = 1, VCC = 5.0V Condition Min. 3.00
- - -
Standard Typ. Max. 3.30 3.60 40 600 -
- - 100
Unit V
s
td(E-A)
nA s
NOTES: 1. The measurement condition is VCC = AVCC = 2.7V to 5.5V and Topr = -40C to 85 C. 2. Time until the voltage monitor 2 interrupt request is generated since the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to "1" again after setting the VCA27 bit in the VCA2 register to "0". 4. Hold Vdet2 > Vdet1.
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19. Electrical Characteristics
Table 19.8
Symbol
Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset )
Parameter Condition Min. - - Standard Typ. Max. - Vdet1 - 100 Unit V ms
Power-On Reset Valid Voltage -20C Topr < 85C Vpor2 tw(Vpor2-Vdet1) Supply Voltage Rising Time When Power-On Reset is -20C Topr < 85C, Deasserted(1) tw(por2) 0s(3)
NOTES: 1. This condition is not applicable when using with Vcc 1.0V. 2. When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10s, refer to Table 19.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset). 3. tw(por2) is time to hold the external power below effective voltage (Vpor2).
Table 19.9
Symbol Vpor1 tw(Vpor1-Vdet1) tw(Vpor1-Vdet1) tw(Vpor1-Vdet1) tw(Vpor1-Vdet1)
Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset)
Parameter Power-On Reset Valid Voltage Supply Voltage Rising Time When Power-On Reset is Deasserted Supply Voltage Rising Time When Power-On Reset is Deasserted Supply Voltage Rising Time When Power-On Reset is Deasserted Supply Voltage Rising Time When Power-On Reset is Deasserted Condition -20C Topr < 85C 0C Topr 85C, tw(por1) 10s(2) -20C Topr < 0C, tw(por1) 30s(2) -20C Topr < 0C, tw(por1) 10s(2) 0C Topr 85C, tw(por1) 1s(2) Min. - -
- - -
Standard Typ. Max. - 0.1 - 100
- - -
Unit V ms ms ms ms
100 1 0.5
NOTES: 1. When not using the voltage monitor 1 reset, use with Vcc 2.7V. 2. tw(por1) is time to hold the external power below effective voltage (Vpor1).
Vdet1(3) Vccmin Vpor2 Vpor1 tw(por1) tw(Vpor1-Vdet1) Sampling Time(1, 2) tw(por2) tw(Vpor2-Vdet1)
Vdet1(3)
Internal Reset Signal ("L" Valid) 1 x 32 fRING-S 1 x 32 fRING-S
NOTES: 1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time. 2. A sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit for details.
Figure 19.3
Reset Circuit Electrical Characteristics
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19. Electrical Characteristics
Table 19.10
Symbol
- -
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Condition Min. - 7.44 7.04 6.80 Standard Typ. 8
- - -
High-Speed On-Chip Oscillator Frequency VCC = 5.0V, Topr = 25 C When the Reset is Deasserted High-Speed On-Chip Oscillator Frequency 0 to +60 C / 5 V 5 %(2) Temperature * Supplay Voltage Dependence -20 to +85 C / 2.7 to 5.5 V(2)
-40 to +85 C / 2.7 to 5.5 V(2)
Max. - 8.56 8.96 9.20
Unit MHz MHz MHz MHz
NOTES: 1. The measurement condition is VCC = AVCC = 5.0V and Topr = 25 C. 2. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to 00h.
Table 19.11
Symbol td(P-R) td(R-S)
Power Supply Circuit Timing Characteristics
Parameter Condition Min. 1
-
Time for Internal Power Supply Stabilization during Power-On(2) STOP Exit Time(3)
Standard Typ. Max. - 2000
-
Unit
s s
150
NOTES: 1. The measurement condition is VCC = AVCC = 2.7 to 5.5V and Topr = 25 C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until CPU clock supply starts since the interrupt is acknowledged to exit stop mode.
Table 19.12
Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
Timing Requirements of Clock Synchronous Serial I/O (SSU) with Chip Select(1)
Parameter SSCK Clock Cycle Time SSCK Clock "H" Width SSCK Clock "L" Width SSCK Clock Rising Time SSCK Clock Falling Time Conditions Min. 4 0.4 0.4 -
- - -
Standard Typ. -
- - - - - - - - - - - - -
Max. - 0.6 0.6 1 1 1 1 - -
- -
Unit tCYC(2) tSUCYC tSUCYC tCYC(2) s tCYC(2) s ns tCYC(2) ns ns tCYC(2) ns ns
Master Slave Master
Slave SSO, SSI Data Input Setup Time SSO, SSI Data Input Hold Time SCS Setup Time Slave Slave SCS Hold Time SSO, SSI Data Output Delay Time SSI Slave Access Time SSI Slave Out Open Time
100 1 1tCYC+50 1tCYC+50
- - -
1 1.5tCYC+100 1.5tCYC+100
NOTES: 1. VCC = AVCC = 2.7 to 5.5V, VSS = 0V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. 1tCYC = 1/f1(s)
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19. Electrical Characteristics
4-wire bus communication mode, Master, CPHS = "1"
VIH or VOH
SCS(Output)
VIH or VOH tHI tFALL tRISE
SSCK(Output) (CPOS = "1")
tLO tHI
SSCK(Output) (CPOS = "0")
tLO tSUCYC
SSO(Output)
tOD
SSI(Input)
tSU tH
4-wire bus communication mode, Master, CPHS = "0"
VIH or VOH
SCS(Output)
VIH or VOH tHI tFALL tRISE
SSCK(Output) (CPOS = "1")
tLO tHI
SSCK(Output) (CPOS = "0")
tLO tSUCYC
SSO(Output)
tOD
SSI(Input)
tSU tH
CPHS, CPOS : Bits in SSMR register
Figure 19.4
I/O Timing of Clock Synchronous Serial I/O (SSU) with Chip Select (Master)
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19. Electrical Characteristics
4-wire bus communication mode, Slave, CPHS = "1"
VIH or VOH
SCS(Input)
VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK(Input) (CPOS = "1")
tLO tHI
SSCK(Input) (CPOS = "0")
tLO tSUCYC
SSO(Input)
tSU tH
SSI(Output)
tSA tOD tOR
4-wire bus communication mode, Slave, CPHS = "0" SCS(Input)
VIH or VOH VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK(Input) (CPOS = "1")
tLO tHI
SSCK(Input) (CPOS = "0")
tLO tSUCYC
SSO(Input)
tSU tH
SSI(Output)
tSA tOD tOR
CPHS, CPOS : Bits in SSMR register
Figure 19.5
I/O Timing of Clock Synchronous Serial I/O (SSU) with Chip Select (Slave)
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19. Electrical Characteristics
tHI VIH or VOH
SSCK
VIH or VOH tLO tSUCYC
SSO(Output)
tOD
SSI(Input)
tSU tH
Figure 19.6
I/O Timing of Clock Synchronous Serial I/O (SSU) with Chip Select (Clock Synchronous Communication Mode)
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19. Electrical Characteristics
Table 19.13
Symbol VOH
Electrical Characteristics (1) [VCC = 5V]
Parameter Condition IOH = -5mA IOH = -200A Drive capacity HIGH Drive capacity LOW IOL = 5mA IOL = 200A Drive capacity HIGH Drive capacity LOW Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 2.0 - VCC - 0.3 - VCC - 2.0 - VCC - 2.0
- - - - - - - - - - -
Output "H" Voltage
Except XOUT XOUT
IOH = -1mA IOH = -500A
Max. VCC VCC VCC VCC 2.0 0.45 2.0 2.0 0.45 2.0 2.0 1.0
Unit V V V V V V V V V V V V
VOL
Output "L" Voltage
Except P1_0 to P1_3, XOUT P1_0 to P1_3
IOL = 15mA IOL = 5mA IOL = 200A IOL = 1mA IOL = 500A
- - - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0, SSO RESET VI = 5V VI = 0V VI = 0V
0.2
0.2
- -
- - -
2.2 5.0 -5.0 167 - 250 -
V
A A k M
IIH IIL RPULLUP RfXIN fRING-S VRAM
Input "H" current Input "L" current Pull-Up Resistance Feedback XIN Resistance Low-Speed On-Chip Oscillator Frequency RAM Hold Voltage
30 - 40 2.0
50 1.0 125 -
During stop mode
kHz V
NOTES: 1. VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=20MHz, unless otherwise specified.
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19. Electrical Characteristics
Table 19.14
Symbol ICC
Electrical Characteristics (2) [Vcc = 5V] (Topr = -40 to 85 C, unless otherwise specified.)
Parameter Condition High-Speed Mode XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz No division Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock operation VCA26 = VCA27 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock off VCA26 = VCA27 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Min. - Standard Typ. 9 Max. 15 Unit mA
Power Supply Current (VCC=3.3 to 5.5V) In single-chip mode, the output pins are open and other pins are VSS
-
8
14
mA
-
5
-
mA
MediumSpeed Mode
-
4
-
mA
-
3
-
mA
-
2
-
mA
High-Speed On-Chip Oscillator Mode
-
4
8
mA
-
1.5
-
mA
Low-Speed On-Chip Oscillator Mode Wait Mode
-
470
900
A
-
40
80
A
Wait Mode
-
38
76
A
Stop Mode
-
0.8
3.0
A
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19. Electrical Characteristics
Timing Requirements (Unless otherwise specified: VCC = 5V, VSS = 0V at Topr = 25 C) [ VCC = 5V ] Table 19.15
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN Input Cycle Time XIN Input "H" Width XIN Input "L" Width
XIN Input
Parameter Standard Min. Max. 50 - 25 - 25 - Unit ns ns ns
Table 19.16
Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0)
CNTR0 Input, CNTR1 Input, INT1 Input
Parameter CNTR0 Input Cycle Time CNTR0 Input "H" Width CNTR0 input "L" Width Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
Table 19.17
Symbol tc(TCIN) tWH(TCIN) tWL(TCIN)
TCIN Input, INT3 Input
Parameter TCIN Input Cycle Time TCIN Input "H" Width TCIN input "L" Width Standard Min. Max. - 400(1) 200(2) 200(2)
- -
Unit ns ns ns
NOTES: 1. When using Timer C input capture mode, adjust the cycle time ( 1/Timer C count source frequency x 3) or above. 2. When using Timer C input capture mode, adjust the width ( 1/Timer C count source frequency x 1.5) or above.
Table 19.18
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Parameter CLKi Input Cycle Time CLKi Input "H" Width CLKi Input "L" Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RCDi Input Hold Time Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Unit ns ns ns ns ns ns ns
Table 19.19
Symbol tW(INH) tW(INL)
External Interrupt INT0 Input
Parameter INT0 Input "H" Width INT0 Input "L" Width Standard Min. Max. - 250(1) 250(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard. 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard.
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19. Electrical Characteristics
VCC = 5V
tc(CNTR0) tWH(CNTR0) CNTR0 Input tWL(CNTR0)
tc(TCIN) tWH(TCIN) TCIN Input tWL(TCIN) tc(XIN) tWH(XIN) XIN Input tWL(XIN)
tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi Input tW(INH) tsu(D-C) th(C-D)
Figure 19.7
Timing Diagram When VCC = 5V
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19. Electrical Characteristics
Table 19.20
Symbol VOH
Electrical Characteristics (3) [VCC = 3V]
Parameter Condition IOH = -1mA Drive capacity HIGH Drive capacity LOW IOL = 1mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 0.5 - VCC - 0.5 - VCC - 0.5
- - - - - - - -
Output "H" Voltage Except XOUT XOUT
IOH = -0.1mA IOH = -50A
Max. VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 0.8
Unit V V V V V V V V V
VOL
Output "L" Voltage
Except P1_0 to P1_3, XOUT P1_0 to P1_3
IOL = 2mA IOL = 1mA IOL = 0.1mA IOL = 50A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0, SSO VI = 3V VI = 0V VI = 0V
0.2
IIH IIL RPULLUP RfXIN fRING-S VRAM
RESET Input "H" Current Input "L" Current Pull-Up Resistance Feedback XIN Resistance Low-Speed On-Chip Oscillator Frequency RAM Hold Voltage
0.2
- - 66 -
- - - 160 3.0
1.8 4.0 -4.0 500 - 250 -
V
A A k M
During stop mode
40 2.0
125 -
kHz V
NOTES: 1. VCC = AVCC = 2.7 to 3.3V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=10MHz, unless otherwise specified.
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19. Electrical Characteristics
Table 19.21
Symbol ICC
Electrical Characteristics (4) [Vcc = 3V] (Topr = -40 to 85 C, unless otherwise specified.)
Parameter Condition High-Speed Mode XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz No division Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock operation VCA26 = VCA27 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock off VCA26 = VCA27 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Min. - Standard Typ. 8 Max. 13 Unit mA
Power Supply Current (VCC=2.7 to 3.3V) In single-chip mode, the output pins are open and other pins are VSS
-
7
12
mA
-
5
-
mA
MediumSpeed Mode
-
3
-
mA
-
2.5
-
mA
-
1.6
-
mA
High-Speed On-Chip Oscillator Mode
-
3.5
7.5
mA
-
1.5
-
mA
Low-Speed On-Chip Oscillator Mode Wait Mode
-
420
800
A
-
37
74
A
Wait Mode
-
35
70
A
Stop Mode
-
0.7
3.0
A
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19. Electrical Characteristics
Timing requirements (Unless otherwise specified: VCC = 3V, VSS = 0V at Topr = 25 C) [VCC = 3V] Table 19.22
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN Input Cycle Time XIN Input "H" Width XIN Input "L" Width
XIN Input
Parameter Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
Table 19.23
Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0)
CNTR0 Input, CNTR1 Input, INT1 Input
Parameter CNTR0 Input Cycle Time CNTR0 Input "H" Width CNTR0 Input "L" Width Standard Min. Max. 300 - 120 - 120 - Unit ns ns ns
Table 19.24
Symbol tc(TCIN) tWH(TCIN) tWL(TCIN)
TCIN Input, INT3 Input
Parameter TCIN Input Cycle Time TCIN Input "H" Width TCIN Input "L" Width Standard Min. Max. - 1,200(1) 600(2) 600(2)
- -
Unit ns ns ns
NOTES: 1. When using the Timer C input capture mode, adjust the cycle time (1/Timer C count source frequency x 3) or above. 2. When using the Timer C input capture mode, adjust the width (1/Timer C count source frequency x 1.5) or above.
Table 19.25
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Parameter CLKi Input Cycle Time CLKi Input "H" Width CLKi Input "L" Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RCDi Input Hold Time Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Unit ns ns ns ns ns ns ns
Table 19.26
Symbol tW(INH) tW(INL)
External Interrupt INT0 Input
Parameter INT0 Input "H" Width INT0 Input "L" Width Standard Min. Max. - 380(1) 380(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard. 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard.
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19. Electrical Characteristics
VCC = 3V
tc(CNTR0) tWH(CNTR0) CNTR0 Input tWL(CNTR0)
tc(TCIN) tWH(TCIN) TCIN Input tWL(TCIN) tc(XIN) tWH(XIN) XIN Input tWL(XIN)
tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi Input tW(INH) tsu(D-C) th(C-D)
Figure 19.8
Timing Diagram When VCC = 3V
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20. Precautions
20. Precautions
20.1 20.1.1 Stop Mode and Wait Mode Stop Mode
When entering stop mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) and the CM10 bit to "1" (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to "1" (stop mode) and the program stops. Insert at least 4 NOP instructions after inserting the JMP.B instruction immediately after the instruction which sets the CM10 bit to "1". Use the next program to enter stop mode.
* Program to enter stop mode
BCLR BSET BSET JMP.B LABEL_001 : NOP NOP NOP NOP
1,FMR0 0,PRCR 0,CM1 LABEL_001
; CPU rewrite mode disabled ; Protect disabled ; Stop mode
20.1.2
Wait Mode
When entering wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. Also, the value in the specific internal RAM area may be rewritten when exiting wait mode if writing to the internal RAM area before executing the WAIT instruction and entering wait mode. The area for a maximum of 3 bytes is rewritten from the following address of the internal RAM in which the writing is performed before the WAIT instruction. The rewritten value is the same value as the one which was written before the WAIT instruction. If this causes a problem, avoid by inserting the JMP.B instruction between the writing instruction to the internal RAM area and WAIT instruction as shown in the following program example.
* Example to execute the WAIT instruction Program Example MOV.B #055h,0601h ; Write to internal RAM area ... JMP.B LABEL_001 LABEL _001 : FSET I ; Enable interrupt BCLR 1,FMR0 ; CPU rewrite mode disabled WAIT ; Wait mode NOP NOP NOP NOP When accessing any area other than the internal RAM area between the writing instruction to the internal RAM area and execution of the WAIT instruction, this situation will not occur.
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20. Precautions
20.2 20.2.1
Interrupts Reading Address 00000h
Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to "0". If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to "0". This may cause a problem that the interrupt is canceled, or an unexpected interrupt is generated.
20.2.2
SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to "0000h" after reset. Therefore, if an interrupt is acknowledged before setting any value in the SP, the program may run out of control.
20.2.3
External Interrupt and Key Input Interrupt
Either an "L" level or an "H" level of at least 250ns width is necessary for the signal input to the INT0 to INT3 pins and KI0 to KI3 pins regardless of the CPU clock.s
20.2.4
Watchdog Timer Interrupt
Reset the watchdog timer after a watchdog timer interrupt is generated.
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20. Precautions
20.2.5
Changing Interrupt Factor
The IR bit in the interrupt control register may be set to "1" (interrupt requested) when the interrupt factor changes. When using an interrupt, set the IR bit to "0" (no interrupt requested) after changing the interrupt factor. In addition, the changes of interrupt factors include all factors that change the interrupt factors assigned to individual software interrupt numbers, polarities, and timing. Therefore, when a mode change of the peripheral functions involves interrupt factors, edge polarities, and timing, Set the IR bit to "0" (no interrupt requested) after the change. Refer to each peripheral function for the interrupts caused by the peripheral functions. Figure 20.1 shows an Example of Procedure for Changing Interrupt Factor.
Interrupt Factor Change
Disable Interrupt(2, 3)
Change Interrupt Factor (including mode of peripheral functions)
Set the IR bit to "0" (interrupt not requested) using the MOV instruction(3)
Enable Interrupt(2, 3)
Change Completed
IR Bit: The interrupt control register bit of an interrupt whose factor is changed. NOTES : 1. Execute the above setting individually. Do not execute 2 or more settings at once (by one instruction). 2. Use the I flag for the INTi (i=0 to 3) interupt. To prevent interrupt requests from being generated when using peripheral function interupts other than the INTi interrupt, disable the peripheral function before changing the interrupt factor. In this case, use the I flag when all maskable interrupts can be disabled. When all maskable interrupts cannot be disabled, use the ILVL0 to ILVL2 bits of interrupt whose factor is changed. 3. Refer to the 21.2.6 Changing Interrupt Control Register for the instructions to be used and their usage notes.
Figure 20.1
Example of Procedure for Changing Interrupt Factor
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20. Precautions
20.2.6
Changing Interrupt Control Register
(a) Each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register. (b) When changing any interrupt control register after disabling interrupts, be careful with the instructions to be used. When changing any bit other than IR bit If an interrupt request corresponding to that register is generated while executing the instruction, the IR bit may not be set to "1" (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register. Instructions to use: AND, OR, BCLR, BSET When changing IR bit If the IR bit is set to "0" (interrupt not requested), it may not be set to "0" depending on the instruction to be used. Therefore, use the MOV instruction to set the IR bit to "0". (c) When disabling interrupts using the I flag, set the I flag according to the following sample programs. Refer to (b) for the change of interrupt control registers in the sample programs.
Sample programs 1 to 3 are preventing the I flag from being set to "1" (interrupt enables) before changing the interrupt control register for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag being set to "1" before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TXIC register to "00h" NOP ; NOP FSET I ; Enable interrupts Example 2: Use dummy read to have FSET instruction wait INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TXIC register to "00h" MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TXIC register to "00h" POPC FLG ; Enable interrupts
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20. Precautions
20.3 20.3.1
Clock Generation Circuit Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the main clock frequency is below 2MHz, set the OCD1 to OCD0 bits to "00b" (oscillation stop detection function disabled).
20.3.2
Oscillation Circuit Constants
Ask the maker of the oscillator to specify the best oscillation circuit constants on your system.
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20. Precautions
20.4 20.4.1
Timers Timers X and Z
* Timers X and Z stop counting after reset. Set the value to these timers and prescalers before the
count starts. * Even if the prescalers and timers are read out in 16-bit units, these registers are read by 1 byte in the microcomputer. Consequently, the timer value may be updated during the period these two registers are being read.
20.4.2
Timer X
* Do not rewrite the TXMOD0 to TXMOD1 bits, the TXMOD2 and TXS bits simultaneously. * In pulse period measurement mode, the TXEDG bit and TXUND bit in the TXMR register can be
set to "0" by writing "0" to these bits by a program. However, these bits remain unchanged when "1" is written. When using the READ-MODIFY-WRITE instruction for the TXMR register, the TXEDG or TXUND bit may be set to "0" although these bits are set to while the instruction is executed. At the time, write "1" to the TXEDG or TXUND bit which is not supposed to be set to "0" with the MOV instruction. When changing to pulse period measurement mode from other mode, the contents of the TXEDG and TXUND bits are indeterminate. Write "0" to the TXEDG and TXUND bits before the count starts. The TXEDG bit may be set to "1" by the prescaler X underflow which is generated for the first time since the count starts. When using the pulse period measurement mode, leave two periods or more of the prescaler X immediately after count starts, and set the TXEDG bit to "0". The TXS bit in the TXMR register has a function to instruct Timer X to start or stop counting, and a function to indicate the count starts or stops. "0" (count stops) can be read until the following count source is applied after "1" (count starts) is written to the TXS bit while the count is being stopped. If the following count source is applied, "1" can be read from the TXS bit. Do not access registers associated with Timer X (TXMR, PREX, TX, TCSS, TXIC registers) except for the TXS bit until "1" can be read from the TXS bit. The count starts at the following count source after the TXS bit is set to "1". Also, when writing "0" (count stops) to the TXS bit during the count, Timer X stops counting at the following count source. "1" (count starts) can be read by reading the TXS bit until the count stops after writing "0" to the TXS bit. Do not access registers associated with Timer X other than the TXS bit until "0" can be read by the TXS bit after writing "0" to the TXS bit.
*
* * *
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20. Precautions
20.4.3
Timer Z
* Do not rewrite the TZMOD0 to TZMOD1 bits and the TZS bit simultaneously. * In programmable one-shot generation mode and programmable wait one-shot generation mode,
when setting the TZS bit in the TZMR register to "0" (stops counting) or setting the TZOS bit in the TZOC register to "0" (stops one-shot), the timer reloads the value of reload register and stops. Therefore, read the timer count value in programmable one-shot generation mode and programmable wait one-shot generation mode before the timer stops. * The TZS bit in the TZMR register has a function to instruct Timer Z to start or stop counting, and a function to indicate the count starts or stops. "0" (count stops) can be read until the following count source is applied after "1" (count starts) is written to the TZS bit while the count is being stopped. If the following count source is applied, "1" can be read from the TZS bit. Do not access registers associated with Timer Z (TZMR, PREZ, TZSC, TZPR, TZOC, PUM, TCSC, TZIC registers) except for the TZS bit until "1" can be read from the TZS bit. The count starts at the following count source after the TZS bit is set to "1". Also, when writing "0" (count stops) to the TZS bit during the count, Timer Z stops counting at the following count source. "1" (count starts) can be read by reading the TZS bit until the count stops after writing "0" to the TZS bit. Do not access registers associated with Timer Z other than the TZS bit until "0" can be read by the TZS bit after writing "0" to the TZS bit.
20.4.4
Timer C
Access the TC, TM0 and TM1 registers in 16-bit units. The TC register can be read in 16-bit units. This prevents the timer value from being updated between the low-order byte and high-order byte are being read. Example (when Timer C is read): MOV.W 0090H,R0 ; Read out timer C
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20. Precautions
20.5
Serial Interface
* When reading data from the U0RB (i = 0, 1) register even in the clock asynchronous serial I/O mode
or in the clock synchronous serial I/O mode. Ensure to read data in 16-bit unit. When the high-order byte of the U0RB register is read, the PER and FER bits in the U0RB register and the RI bit in the U0C1 register are set to "0". Example (when reading receive buffer register): MOV.W 00A6H,R0 ; Read the U0RB register
* When writing data to the U0TB register in the clock asynchronous serial I/O mode with 9-bit transfer
data length, write data high-order byte first, then low-order byte in 8-bit units. Example (when reading transmit buffer register): MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
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20. Precautions
20.6 20.6.1
Clock Synchronous Serial I/O (SSU) with Chip Select Access Registers Associated with SSU
After the conditions of "3 instructions or more after writing to the registers associated with SSU (00B8h to 00BFh)" or "4 cycles or more after writing to them" are met, read those registers.
* An example to wait for 3 instructions or more
MOV.B NOP NOP NOP MOV.B * An example to wait for 4 cycles or more Program Example BCLR JMP.B NEXT: BEST Program Example #00h,00BBh ; Set the SSER register to "00h".
00BBh,R0L 4,00BBh NEXT 3,00BBh : Disable transmit
: Enable receive
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20. Precautions
20.7
A/D Converter
* Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the
SMP bit in the ADCON2 register when the A/D conversion stops (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from "0" (VREF not connected) to "1" (VREF connected), wait for at least 1s or longer before the A/D conversion starts. When changing A/D operating mode, select an analog input pin again. When using in one-shot mode. Ensure that the A/D conversion is completed and read the AD register. The IR bit in the ADIC register or the ADST bit in the ADCON0 register can determine whether the A/D conversion is completed. When using In repeat mode, use the undivided main clock for the CPU clock. If setting the ADST bit in the ADCON0 register to "0" (A/D conversion stops) by a program and the A/ D conversion is forcibly terminated during the A/D conversion operation, the conversion result of the A/D converter will be indeterminate. If the ADST bit is set to "0" by a program, do not use the value of AD register. Connect 0.1F capacitor between the AVCC/VREF pin and AVSS pin.
* *
* *
*
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20. Precautions
20.8 20.8.1
Flash Memory Version CPU Rewrite Mode Operating Speed
20.8.1.1
Before entering CPU rewrite mode (EW0 mode), select 5MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1 mode.
20.8.1.2
Instructions Inhibited Against Use
The following instructions cannot be used in EW0 mode because the flash memory internal data is referenced: UND, INTO, and BRK instructions.
20.8.1.3
Interrupts
Table 20.1 lists the Interrupt in EW0 Mode and Table 20.2 lists the Interrupt in EW1 Mode.
Table 20.1 Interrupt in EW0 Mode
Mode
When maskable When watchdog timer, oscillation stop detection and interrupt request is voltage monitor 2 interrupt request are acknowledged acknowledged EW0 During automatic Any interrupt can be Once an interrupt request is acknowledged, the autoerasing used by allocating a programming or auto-erasing is forcibly stopped immediately and resets the flash memory. An interrupt vector to RAM process starts after the fixed period and the flash memory restarts. Since the block during the auto-erasing or the address during the auto-programming is forcibly stopped, the normal value may not be read. Execute the Automatic writing auto-erasing again and ensure the auto-erasing is completed normally. Since the watchdog timer does not stop during the command operation, the interrupt request may be generated. Reset the watchdog timer regularly. Status
NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while Block 0 is automatically erased because the fixed vector is allocated Block 0.
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R8C/14 Group, R8C/15 Group
20. Precautions
Table 20.2
Interrupt in EW1 Mode
Mod e
Status
EW1 During automatic erasing (erasesuspend function is enabled)
During automatic erasing (erasesuspend function is disabled)
Auto programming
When watchdog timer, oscillation stop detection and voltage monitor 2 interrupt request are acknowledged Once an interrupt request is acknowledged, The auto-erasing is suspended the auto-programming or auto-erasing is after td(SR-ES) and the interrupt forcibly stopped immediately and resets the process is executed. The autoerasing can be restarted by setting flash memory. An interrupt process starts after the fixed period and the flash memory the FMR41 bit in the FMR4 register to "0"(erase restart) after restarts. Since the block during the autoerasing or the address during the autothe interrupt process completes. programming is forcibly stopped, the The auto-erasing has a priority normal value may not be read. Execute the and the interrupt request acknowledgement is waited. The auto-erasing again and ensure the autointerrupt process is executed after erasing is completed normally. the auto-erasing completes. Refer Since the watchdog timer does not stop during the command operation, the to 20.8.1.9 Interrupt Request interrupt request may be generated. Reset Generation during Auto-erase the watchdog timer regularly using the Operation in EW1 Mode. erase-suspend function. The auto-programming has a priority and the interrupt request acknowledgement is waited. The interrupt process is executed after the auto-programming completes. When maskable interrupt request is acknowledged
NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while Block 0 is automatically erased because the fixed vector is allocated Block 0.
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
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R8C/14 Group, R8C/15 Group
20. Precautions
20.8.1.4
How to Access
Write "0" to the corresponding bits before writing "1" when setting the FMR01, FMR02, or FMR11 bit to "1". Do not generate an interrupt between writing "0" and "1".
20.8.1.5
Rewriting User ROM Area
In EW0 Mode, if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, the flash memory may not be able to be rewritten because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode.
20.8.1.6
Program
Do not write additions to the already programmed address.
20.8.1.7
Reset Flash Memory
When setting the FMSTP bit in the FMR0 register to "1" (flash memory stops) during erase-suspend in EW1 mode, a CPU stops and cannot return. Do not set the FMSTP bit to "1".
20.8.1.8
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
20.8.1.9
Interrupt Request Generation during Auto-erase Operation in EW1 Mode
When an interrupt request is generated during erasing with FMR01 = 1 (CPU rewrite mode enabled) in FMR0 register, FMR11 = 1 (EW1 mode) in FMR1 register and FMR40 = 0 (disable erase suspend function) in FMR4 register, the CPU may not operate properly. Select any of the following 3 processes as a software countermeasure: (a) Disable an interrupt by setting the priority level of all maskable interrupts to level 0. Note that disabling the interrupts by the I flag will not be in the software countermeasure (b) Set the FMR40 = 1 (enable erase suspend function) and the I flag = 1 (enable interrupt) when using the FMR11 = 1 (EW1 mode) (c) Use EW0 mode.
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
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R8C/14 Group, R8C/15 Group
20. Precautions
20.9 20.9.1
Noise Insert a bypass capacitor between VCC and VSS pins as the countermeasures against noise and latch-up
Connect the bypass capacitor (at least 0.1F) using the shortest and thickest as possible.
20.9.2
Countermeasures against Noise Error of Port Control Registers
During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may be changed. As a firmware countermeasure, it is recommended to periodically reset the port registers, port direction registers and pull-up control registers. However, examine fully before introducing the reset routine as conflicts may be created between this reset routine and interrupt routines.
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
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R8C/14 Group, R8C/15 Group
21. Precaution for On-chip Debugger
21. Precaution for On-chip Debugger
When using the on-chip debugger to develop the R8C/14 and R8C/15 groups program and debug, pay the following attention. (1) (2) (3) (4) Do not use from OC000h address to OC7FFh because the on-chip debugger uses these addresses. Do not set the address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system. Do not use the BRK instruction in a user system. The stack pointer with up to 8 bytes is used during the user program break. Therefore, save space of 8 bytes for the stack area.
Connecting and using the on-chip debugger has some peculiar restrictions. Refer to each on-chip debugger manual for on-chip debugger details.
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
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R8C/14 Group, R8C/15 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A MASS[Typ.] 0.1g
20
11
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1
Index mark
10
c
A2
A1
*2
D
Reference Symbol
Dimension in Millimeters
e y
*3
bp Detail F
D E A2 A A1 bp c HE e y L
Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0.1 0.2 0 0.17 0.22 0.32 0.13 0.15 0.2 0 10 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
A
Page 250 of 253
L
Min 6.4 4.3
R8C/14 Group, R8C/15 Group Appendix 2. Connecting Example between Serial Writer and On-Chip Debugging
Appendix 2. Connecting Example between Serial Writer and On-Chip Debugging Emulator
Appendix Figure 2.1 shows the Connecting Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows the Connecting Example with Emulator E8 (R0E000080KCE00).
(2)
1 2 (3)
20 19 18
TXD RESET Connect Oscillation Circuit(1) VSS
3
R8C/14, 15 Group
4 5 6 7
17 16 15 14 13 12 11
VCC
MODE
8 9 10
10 TXD 7 VSS
RXD 4 1 VCC
M16C Flash Starter (M3A-0806)
(2)
RXD NOTES: 1. Need to connect an oscillation circuit, even when operating with the on-chip oscillator clock. 2. For development tools only. 3. Connect the external reset circuit.
Appendix Figure 2.1
Connecting Example with M16C Flash Starter (M3A-0806)
1 2 3
20 19 18
R8C/14, 15 Group
User Reset Signal VSS
Connect Oscillation Circuit(1)
4 5 6 7 8
17 16 15 14 13 12 11
VCC
14 12 10 8 VCC 6 4 2 VSS
13 RESET
4.7k MODE
9 10
7 MODE
Emulator E8 (R0E000080KCE00)
NOTES: 1. No need to connect an oscillation circuit when operating with the on-chip oscillator clock.
Appendix Figure 2.2
Connecting Example with Emulator E8 (R0E000080KCE00)
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
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R8C/14 Group, R8C/15 Group
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows the Example of Oscillation Evaluation Circuit.
1 2
20 19 18 17 16 15 14 13 12 11 VCC
R8C/14, R8C/15 Group
RESET Connect Oscillation Circuit
3 4
VSS
5 6 7 8 9 10
NOTES: 1. Set a program before evaluating.
Appendix Figure 3.1 Example of Oscillation Evaluation Circuit
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
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R8C/14 Group, R8C/15 Group
Register Index
Register Index
A
AD .......................................... 171 ADCON0 ................................. 170 ADCON1 ................................. 170 ADCON2 ................................. 171 ADIC ........................................ 61 AIER ......................................... 77
P
P1 ..........................................184 P3 ..........................................184 P4 ..........................................184 PD1 ........................................184 PD3 ........................................184 PD4 ........................................184 PM0 ..........................................35 PM1 ..........................................36 PRCR .......................................55 PREX .......................................86 PREZ ......................................100 PUM .......................................101 PUR0 ......................................185 PUR1 ......................................185
U
U0BRG ...................................127 U0C0 ......................................128 U0C1 ......................................129 U0MR .....................................128 U0RB ......................................127 U0TB ......................................127 UCON .....................................129
C
CM0 ......................................... 40 CM1 ......................................... 41 CMP0IC .................................... 61 CMP1IC .................................... 61 CSPR ....................................... 80
V
VCA1 ........................................28 VCA2 ........................................28 VW1C .......................................29 VW2C .......................................30
D
DRR ....................................... 185
R
RMAD0 .....................................77 RMAD1 .....................................77
W
WDC .........................................79 WDTR .......................................80 WDTS .......................................80
F
FMR0 ..................................... 200 FMR1 ..................................... 201 FMR4 ..................................... 201
S
S0RIC .......................................61 S0TIC .......................................61 SSCRH ...................................142 SSCRL ...................................143 SSER .....................................145 SSMR .....................................144 SSMR2 ...................................147 SSRDR ...................................148 SSSR .....................................146 SSTDR ...................................148 SSUAIC ....................................61
H
HRA0 ....................................... 43 HRA1 ....................................... 44 HRA2 ....................................... 44
I
INT0F ....................................... 69 INT0IC ...................................... 62 INT1IC ...................................... 61 INT3IC ...................................... 61 INTEN ...................................... 69
T
TC ..........................................117 TCC0 ......................................118 TCC1 ......................................119 TCIC .........................................61 TCOUT ...................................120 TCSS ................................86, 102 TM0 ........................................117 TM1 ........................................117 TX ............................................86 TXIC .........................................61 TXMR .......................................85 TZIC .........................................61 TZMR .......................................99 TZOC .....................................101 TZPR ......................................100 TZSC ......................................100
K
KIEN ......................................... 75 KUPIC ...................................... 61
O
OCD ......................................... 42 OFS ................................. 79, 196
Rev.2.10 Jan 19, 2006 REJ09B0164-0210
Page 253 of 253
REVISION HISTORY REVISION HISTORY
Rev. 0.10 0.20 0.30 Date May 17, 2004 Jul 12, 2004 Aug 06, 2004
R8C/14 Group, R8C/15 Group Hardware
Description
Page
- -
Summary First Edition issued Rev.0.20 issued Words standardized (on-chip oscillator, serial interface, SSU) Table 1.1 revised Table 1.2 revised Table 1.5 revised Table 1.6 added "Address Break" in Figures 3.1 and 3.2 ; notes added Table 4.1, HRA2 Register at 0022h added ; NOTE2 to 6 revised Table 4.3 the value after reset to FFh at 009Ch to 009Fh revised Tabel 4.4, the value after reset to FFh at 009Ch to 009Fh revised ; NOTES added Compositions and contents of "5. Reset" modified Compositions and contents of "6. Voltage Detection Circuit" modified Figure 7.2, function of b0 revised Figure 9.1 revised Figure 9.2, "System" at CM06 bit added Figure 9.3, "System" at CM16 and CM17 bits added Figure 9.5 revised 9.2.2, "The oscillation starts...HRA2 registers" added 9.3.1 added 9.3.3 "The clock...divided-by-i"added Table 9.4 revised 11.1.3.4, "Address Break Interrup" added ; the referred distination to "20. On-Chip Debugger" revised Table 11.1, some referred distinations revised Table 11.2, some referred distinations revised Figures 11.7 and 11.8 added 11.2.1, "The INT0 pin...timer Z" added 11.2.3, "The INT0 pin...CNTR01 pin" added 11.2.4, "The INT3 pin is used with the TCIN pin" added Compositions and contents of "12. Watchdog Timer" modified Figure 13.2 revised Table 13.2 revised Table 13.3 revised Figure 13.5 revised Table 13.4 revised Figure 13.6 revised Table 13.5 revised Figure 13.7 revised Table 13.6 revised Figure 13.9 revised Figure 13.10 revised 13.2 revised Table 13.7 revised Table 13.8 revised
all pages 2 3 9 10 14,15 16 18 19 20-25 26-35 37 40 41 42 44 47 48 52 60 61 62 68 72 74 75 80-84 87 89 90 91 92 93 94 95 97 98 99 100 105 107
C-1
REVISION HISTORY
Rev. 0.30 Date Aug 06, 2004
R8C/14 Group, R8C/15 Group Hardware
Description
Page 110 112 114 118 119 121 123 125 130 131 136 138 140 141 143 144 146 148 152 154 159 162 164 165 167 171 174 175 176 178 179 180 184 185 186 188 89 190 191 193 195
Summary
Table 13.9 revised Figure 13.20 revised Table 13.10 revised Figure 13.25 revised Figure 13.26 revised Figure 13.28 revised Table 13.11 revised Table 13.12 revised Figure 14.4 revised Figure 14.5 revised 14.1.3 revised Table 14.5, NOTES revised Figure 14.10 revised ; 14.2.1 "input" added 14.2.2 added Figure 15.1 revised Figure 15.2 revised Figure 15.4 revised Figure 15.6 revised Figure 15.9 revised 15.3 revised Figure 15.14 revised 15.6 revised 15.6.2 revised Figure 15.18 revised Figure 15.19 revised Figure 16.2 revised Figure 16.4 revised Table 16.3 revised Figure 16.5 revised 17.1.4 revised Figure 17.1 revised Figure 17.2 revised Figure 17.8 revised Table 17.1 revised Table 18.1 revised 18.2 revised Figure 18.2, NOTES revised Figure 18.3 ID5 and 6 revised 18.3.2 revised ; "After Reset" revised to "Before Shipment" 18.4.1 and 18.4.2 revised 18.4.2.11 and 18.4.2.12 revised Figure 18.5 revised 196 Figure 18.6 revised 198 Figure 18.9 revised 204 Table 18.6 revised 210-223 "19. Electrical Characteristics" added 230 21.1 "Stop Mode and Wait Mode" revised 240 21.7.1.8 revised 21.7.1.9 added 244 "Appendix 2. Connecting Example between Serial Writer and On-Chip Debugging Emulator" added 247 "Appendix 3. Example of Oscillation Evaluation Circuit" added C-2
REVISION HISTORY
Rev. 1.00 Date Feb 25, 2005
R8C/14 Group, R8C/15 Group Hardware
Description
Page 2-3 5 6 7-8 16
Summary
Tables 1.1 and 1.2 revised Table 1.3 and figure 1.2 revised Table 1.4 and figure 1.3 revised Figures 1.4 and 1.5 revised Tabel 4.1, The value after reset to 000XXXXXb to 00011111b at 000Fh; and the value after reset to 00001000b to 0000X000b and 01001001b to 0100X001b at 0036h revised 18 Tabel 4.3, The value after reset to 0000h at 009Ch to 009Dh revised; NOTES2 added, and the value after reset to 00h at 00BCh revised 20 Figure 5.1 revised 22 5.1.1 (2) and 5.1.2 (4) revised 24 5.2 revised Figure 5.6 revised 25 5.3 revised 26 Table 6.1 revised 27 Figures 6.1 and 6.2 revised 29 Figure 6.4 revised 30 Figure 6.5 revised 31 Figure 6.6 revised 32 6.1.1 revised 33 Table 6.2 and figure 6.7 revised 34 Table 6.3 revised 35 Figure 6.8 revised 37 Figure 7.2 revised 39 Table 9.1 revised; NOTE2 added 40 Figure 9.1 revised 41 Figure 9.2 revised 42 Figure 9.3 revised 44 Figure 9.5 revised 51 Table 9.3 revised 52 Table 9.4 revised 55 9.5 and 9.5.1 revised Table 9.5 revised 60 11.1.3.5 revised 61 Table 11.1 revised 68 11.1.6.7 revised 71 Figure 11.11 "INTEN Register" revised 78-79 11.4 "Address Match Interrupt", Table 11.6, 11.7 and Figure 11.19 added 81 Figure 12.2 "WDC Register" revised 83 Table 12.1 revised 89-96 Table 13.2, 13.3, 13.4, 13.5 and 13.6 revised; "Write to Timer" revised 104 Table 13.7 revised 106-113 Table 13.8, 13.9 and 13.10 revised 118 Figure 13.26 revised 126 Figure 14.1 revised 129 Figure 14.4 "U0C0 Register" revised 130 Figure 14.5 "UCON Register" revised 131 14.1 revised 137 Table 14.6 revised
C-3
REVISION HISTORY
Rev. 1.00 Date Feb 25, 2005
R8C/14 Group, R8C/15 Group Hardware
Description Summary Table 15.1 NOTE2 added Figure 15.4 NOTES added Figure 15.6 revised; The value after reset to 00h Figure 15.8 revised 15.2 revised; "15.2 SS Shift Register" added and 15.2 revised to 15.5.2 Figure 15.13 NOTE2 added Figure 15.14 revised 15.5.4 revised 15.6 revised Figure 15.17 revised 15.6.2 revised 15.6.4 revised Table 16.1 revised Figures 16.2, 16.4 and 16.5 revised 17.1, 17.2 and 17.3 revised; Tables 17.1, 17.2 and 17.3 added Table 17.4 revised Figure 17.9 added 188-189 Figures 18.1 and 18.2 revised 191 18.3.2 revised 192 Table 18.3 revised 202 Figure 18.12 revised 207 Figure 18.14 revised 211 Table 19.3 revised 212 Table 19.4 and 19.5 revised 213 Figure 19.2, Tables 19.6 and 19.7 revised 214 Tables 19.8 and 19.9 revised 215 Table 19.10, 19.11 revised and Table 19.12 added 216-218 Figures 19.4, 19.5 and 19.6 added 219 Table 19.13 revised 220 Table 19.14 revised 221, 225 Table 19.16 and 19.23 revised: Table title "INT2" "INT1" Table 19.20 NOTE revised 223 Table 19.21 revised 224 20.1.1 and 20.1.2 revised 227 20.4.2 revised 232 20.4.3 revised 233 20.6 added 235 20.7 revised 236 20.8.1.7 and 20.8.1.8 revised 239 "20. On-chip Debugger" deleted 241 Appendix Package Dimensions revised 242 Appendix Figure 2.1 revised; "USB Flash Writer" deleted and "M16C 243 Flash Starter" NOTE3 added Page 141 145 147 149 152 157 158 160 162 163 164 168 169 171-176 178 185
C-4
REVISION HISTORY REVISION HISTORY
Rev. 2.00 Date Jan 12, 2006
R8C/14 Group, R8C/15 Group Hardware R8C/14 Group, R8C/15 Group Hardware
Description
Page 1 2 3
Summary 1. Overview; "20-pin plastic molded LSSOP or SDIP" "20-pin plastic molded LSSOP" revised Table 1.1 Performance Outline of the R8C/14 Group; Package: "20-pin plastic molded SDIP" deleted Table 1.2 Performance Outline of the R8C/15 Group; Package: "20-pin plastic molded SDIP" deleted, Flash Memory: (Data area) (Data flash) (Program area) (Program ROM) revised Figure 1.1 Block Diagram; "Peripheral Function" added, "System Clock Generation" "System Clock Generator" revised Table 1.3 Product Information of R8C/14 Group, Table 1.4 Product Information of R8C/15 Group; revised. Figure 1.2 Part Number, Memory Size and Package of R8C/14 Group, Figure 1.3 Part Number, Memory Size and Package of R8C/15 Group; Package type: "DD : PRDP0020BA-A" deleted Figure 1.5 PRDP0020BA-A Package Pin Assignment (top view) deleted Table 1.5 Pin Description; Timer C: "CMP0_0 to CMP0_3, CMP1_0 to CMP1_3" "CMP0_0 to CMP0_2, CMP1_0 to CMP1_2" revised Figure 2.1 CPU Register; "Reserved Area" "Reserved Bit" revised 2.8.10 Reserved Area; "Reserved Area" "Reserved Bit" revised Figure 3.1 Memory Map of R8C/14 Group revised 3.2 R8C/15 Group, Figure 3.2 Memory Map of R8C/15 Group revised Table 4.1 SFR Information(1); 0009h: "XXXXXX00b" "00h" 000Ah: "00XXX000b" "00h" 001Eh: "XXXXX000b" "00h" Table 4.3 SFR Information(3); 0085h: "Prescaler Z" "Prescaler Z Register" 0086h: "Timer Z Secondary" "Timer Z Secondary Register" 0087h: "Timer Z Primary" "Timer Z Primary Register" 008Ch: "Prescaler X" "Prescaler X Register" 008Dh: "Timer X" "Timer X Register" 0090h, 0091h: "Timer C" "Timer C Register" revised Figure 5.3 Reset Sequence revised 5.2 Power-On Reset Function; "When a capacitor is connected to ... 0.8VCC or more." added Figure 6.5 VW1C Register revised Figure 6.6 VW2C Register NOTE10 added
4
5, 6
8
10 12 13 14 15
17
20 23 29 30
C-5
REVISION HISTORY
R8C/14 Group, R8C/15 Group Hardware
Description
Rev. 2.00
Date Jan 12, 2006
Page 32 33 37
Summary Table 6.2 Setting Procedure of Voltage Monitor 1 Reset Associated Bit revised Table 6.3 Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bit revised Table 8.2 Bus Cycles for Access Space of the R8C/15 Group added, Table 8.3 Access Unit and Bus Operation; "SFR" "SFR, Data flash", "ROM/RAM" "ROM (Program ROM), RAM" revised Table 9.1 Specification of Clock Generation Circuit NOTE2 deleted Figure 9.1 Clock Generation Circuit revised Figure 9.2 CM0 Register NOTE2 revised Figure 9.4 OCD Register NOTES 3, 4 revised Figure 9.5 HRA0 Register NOTE2 revised 9.1 Main Clock; "After reset, ..." "During reset and after reset, ..." revised 9.2.1 Low-Speed On-Chip Oscillator Clock; "The application ... to accommodate the frequency range." "The application ... for the frequency change." 9.3.2 CPU Clock; "When changing the clock source ... the OCD2 bit." deleted 9.4.1 Normal Operating Mode; "... into three modes" "... into four modes" revised Table 9.2 Setting and Mode of Clock Associated Bit revised 9.4.1.1 High-Speed Mode, 9.4.1.2 Medium-Speed Mode; "Set the CM06 bit to "1" ... on-chip oscillator mode." deleted 9.4.1.3 High-Speed, Low-Speed On-Chip Oscillator Mode; "9.4.1.3 On-Chip Oscillator Mode" "9.4.1.3 High-Speed, Low-Speed On-Chip Oscillator Mode" revised, "Set the CM06 bit to "1" ... high-speed and medium-speed." deleted Figure 9.8 State Transition to Stop and Wait Modes; "Figure 9.8 State Transition to Stop and Wait Modes" "Figure 9.8 State Transition of Power Control" revised Figure 9.9 State Transition in Normal Operating Mode deleted 9.5.1 How to Use Oscillation Stop Detection Function; "* This function cannot ... is 2 MHz or below. ..." "* This function cannot ... is below 2 MHz. ..." revised Figure 9.9 Procedure of Switching Clock Source From Low-Speed OnChip Oscillator to Main Clock revised Figure 10.1 PRCR Register "00XXX000b" "00h" revised
Figure 11.10 Judgement Circuit of Interrupts Priority Level NOTE1 deleted
38 39 40 42 43 45 46
47 48
49
52
53
54 55 68 69
Figure 11.11 INTEN and INT0F Registers; INT0F Register "XXXXX000b" "00h" revised
C-6
REVISION HISTORY
R8C/14 Group, R8C/15 Group Hardware
Description
Rev. 2.00
Date Jan 12, 2006
Page 76
Summary 11.4 Address Match Interrupt; "... , do not use an address match interrupt in a user system." "... , do not set an address match interrupt (the registers of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system." revised Figure 11.19 AIER, RMAD0 to RMAD1 Registers; AIER Register revised Figure 12.2 OFS and WDC Registers; * Option Function Select Register NOTE1 revised, NOTE2 added * Watchdog Timer Control Register NOTE1 deleted Table 13.1 Functional Comparison of Timers; "Decrement" "Increment" Figure 13.1 Block Diagram of Timer X revised Table 13.2 Specification of Timer Mode; * "INT1/CNTR0 Signal Pin Function" "INT10/CNTR00, INT11/CNTR01 Pin Function" revised * "* When writing ... registers (the data is transferred to the counter when the following count source is input)." "* When writing ... registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input." revised Table 13.3 Specification of Pulse Output Mode; * "INT1/CNTR0 Signal Pin Function" "INT10/CNTR00 Pin Function" revised * "* When writing ... registers (the data is transferred to the counter when the following count source is input)." "* When writing ... registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input." revised * NOTE1 added
77 79
83 84 87
88
90, 92, 95 Table 13.4 Specification of Event Counter Mode, Table 13.5 Specification of Pulse Width Measurement Mode, Table 13.6 Specification of Pulse Period Measurement Mode; * "INT1/CNTR0 Signal Pin Function" "INT10/CNTR00, INT11/CNTR01 Pin Function" revised * "* When writing ... registers (the data is transferred to the counter when the following count source is input)." "* When writing ... registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input." revised 98 101 Figure 13.11 Block Diagram of Timer Z; "Peripheral Data Bus" "Data Bus" revised Figure 13.14 TZOC and PUM Registers; Timer Z Output Control Register "Stops counting" "One-shot stops", "Starts counting" "One-shot starts" revised
C-7
REVISION HISTORY
R8C/14 Group, R8C/15 Group Hardware
Description
Rev. 2.00
Date Jan 12, 2006
Page 103
Summary Table 13.7 Specification of Timer Mode; "* When writing ... registers (the data is transferred to the counter when the following count source is input) while the TZWC bit is set to "0" (writing to the reload register and counter simultaneously)." "* When writing ... registers at the following count source input and the data is transferred to the counter at the second count source input and the count re-starts at the third count source input." revised
108, 112 Table 13.9 Specification of Programmable One-Shot Generation Mode, Table 13.10 Specification of Programmable Wait One-Shot Generation Mode Specifications; Count Operation; "* When a count completes, ..." "* When a count stops, ..." revised 112
Table 13.10 Specification of Programmable Wait One-Shot Generation Mode Specifications; NOTE1, 2, 3 revised
116 123 124 127 128 136 169
Figure 13.25 Block Diagram of CMP Waveform Output Unit revised Table 13.12 Specification of Output Compare Mode NOTE1 revised Figure 13.31 Operating Example of Timer C in Output Compare Mode revised Figure 14.3 U0TB, U0RB and U0BRG Registers; U0TB and U0RB Registers revised, U0BRG Register NOTE3 added Figure 14.4 U0MR and U0C0 Registers; U0C0 Register NOTE1 added Table 14.5 Registers to Be Used and Settings in UART Mode; U0BRG: "-" "0 to 7" revised Figure 16.1 Block Diagram of A/D Converter "Vref" "Vcom" revised
170, 173, Figure 16.2 ADCON0 and ADCON1 Registers, 175 Figure 16.4 ADCON0 and ADCON1 Registers in One-Shot Mode, Figure 16.5 ADCON0 and ADCON1 Registers in Repeat Mode; ADCON0 Register revised 176 to 178 Figure 16.6 Timing Diagram of A/D Conversion revised and 16.4 A/D Conversion Cycles to 16.6 Inflow Current Bypass Circuit added
180, 181 Figure 17.1 Configuration of Programmable I/O Ports (1), Figure 17.2 Configuration of Programmable I/O Ports (2); NOTE1 added 182 184 185 186 to 189 191 Figure 17.3 Configuration of Programmable I/O Ports (3) NOTE4 added Figure 17.5 PD1, PD3 and PD4 Registers, Figure 17.6 P1, P3 and P4 Registers; NOTE1, 2 revised Figure 17.7 PUR0 and PUR1 Registers revised 17.4 Port setting added, Table 17.4 Port P1_0/KI0/AN8/CMP0_0 Setting to Table 17.17 Port P4_5/INT0 Setting added Table 18.1 Flash Memory Version Performance; Program and Erase Endurance: (Program area) (Program ROM), (Data area) (Data flash) revised
C-8
REVISION HISTORY
R8C/14 Group, R8C/15 Group Hardware
Description
Rev. 2.00
Date Jan 12, 2006
Page 193
Summary 18.2 Memory Map; "The user ROM ... area ... Block A and B." "The user ROM ... area (program ROM) ... Block A and B (data flash)." revised Figure 18.1 Flash Memory Block Diagram for R8C/14 Group revised Figure 18.2 Flash Memory Block Diagram for R8C/15 Group revised Figure 18.4 OFS Register; NOTE1 revised, NOTE2 added Figure 18.5 FMR0 Register; NOTE6 revised Figure 18.6 FMR1 and FMR4 Registers; FMR4 Register NOTE2 revised Figure 18.7 Timing on Suspend Operation added Figure 18.8 How to Set and Exit EW0 Mode and Figure 18.9 How to Set and Exit EW1 Mode revised Figure 18.13 Block Erase Command (When Using Erase-Suspend Function) revised Figure 18.14 Full Status Check and Handling Procedure for Each Error revised 18.5 Standard Serial I/O Mode revised Figure 18.15 Pin Connections for Standard Serial I/O Mode 3; Figure title revised Figure 18.16 Pin Process in Standard Serial I/O Mode Figure 18.16 Pin Process in Standard Serial I/O Mode 2 revised, Figure 18.17 Pin Process in Standard Serial I/O Mode 3 added Table 19.4 Flash Memory (Program ROM) Electrical Characteristics; * NOTES 1 to 7 added * "Topr" = "Ambient temperature" Table 19.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics; * revised * "Topr" = "Ambient temperature" Figure 19.2 Time delay from Suspend Request until Erase Suspend revised Table 19.8 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset ) NOTE2 revised. Table 19.12 Timing Requirements of Clock Synchronous Serial I/O (SSU) with Chip Select revised. Table 19.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics revised Figure 19.4 I/O Timing of Clock Synchronous Serial I/O (SSU) with Chip Select (Master) revised Figure 19.5 I/O Timing of Clock Synchronous Serial I/O (SSU) with Chip Select (Slave) revised Table 19.13 Electrical Characteristics (1) [VCC = 5V] revised C-9
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REVISION HISTORY
R8C/14 Group, R8C/15 Group Hardware
Description
Rev. 2.00
Date Jan 12, 2006
Page 228 229 231 232 233 239 Table 19.18 Serial Interface; "35" "50", "80" "50"
Summary Table 19.14 Electrical Characteristics (2) [Vcc = 5V] NOTE1 deleted
Table 19.20 Electrical Characteristics (3) [VCC = 3V] revised Table 19.21 Electrical Characteristics (4) [Vcc = 3V] NOTE1 deleted Table 19.25 Serial Interface; "55" "70", "160" "80" 20.3.1 Oscillation Stop Detection Function; "Since ... is 2MHz or below, .." "Since ... is below 2 MHz, .." revised 20.3.2 Oscillation Circuit Constants added 20.4.2 Precautions on Timer X; `* ... When writing "1" (count starts) to ... writing "1" to the TXS bit.' `* ... "0" (count stops) can be ... after the TXS bit is set to "1".' revised 20.4.3 Precautions on Timer Z; * "* In programmable ... "0" and the timer ..." "* In programmable ... "0" (stops counting) or setting the TZOS bit in the TZOC register to "0" (stops one-shot), the timer ..." revised * `* ... When writing "1" (count starts) to ... writing "1" to the TZS bit.' `* ... "0" (count stops) can be ... after the TZS bit is set to "1".' revised Table 20.2 Interrupt in EW1 Mode revised 20.8.1.9 Interrupt Request Generation During Auto-erase Operation in EW1 Mode added 21. Precaution for On-chip Debugger (2) revised, (4) added Appendix 1. Package Dimensions; Package "PRDP0020BA-A" deleted Appendix Figure 2.1 Connecting Example with M16C Flash Starter (M3A-0806); * NOTE1 revised * Pulled up added Table 19.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics; High-Speed On-Chip Oscillator Frequency Temperature * Supplay Voltage Dependence 0 to +60 C / 5 V 5 % Standard Max. "8.16" "8.56" 20.8.1.9 Interrupt Request Generation during Auto-erase Operation in EW1 Mode; (b) revised
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2.10
Jan 19, 2006
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C - 10
R8C/14 Group, R8C/15 Group Hardware Manual Publication Data : Rev.0.10 Rev.2.10 May 17, 2004 Jan 19, 2006
Published by : Sales Strategic Planning Div. Renesas Technology Corp.
(c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan
R8C/14 Group, R8C/15 Group Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

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